Deep Learning Scheduling on a Field-Programmable Gate Array Cluster Using Configurable Deep Learning Accelerators

Deep Learning Scheduling on a Field-Programmable Gate Array Cluster Using Configurable Deep Learning Accelerators

This paper presents the development and evaluation of a distributed system employing low-latency embedded field-programmable gate arrays (FPGAs) to optimize scheduling for deep learning (DL) workloads and to configure multiple deep learning accelerator (DLA) architectures. Aimed at advancing FPGA ap...

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Bibliographic Details
Main Authors: Tianyang Fang, Alejandro Perez-Vicente, Hans Johnson, Jafar Saniie
Format: Article
Language:English
Published: MDPI AG 2025-04-01
Series:Information
Subjects:
deep learning accelerator (DLA)
deep neural network (DNN)
distributed computing
field-programmable gate array (FPGA)
neural processing unit (NPU)
system-on-chip (SoC)
Online Access:https://www.mdpi.com/2078-2489/16/4/298
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