Feasibility of Cascadable Plasmonic Full Adder
The concept and configuration of a plasmonic cascadable full adder are proposed, whose logic operation is carried out by interference of surface plasmons and whose circuits are formed only with single- and multiple-mode plasmonic waveguides. This full adder is fabricated by patterning a SiO<sub&g...
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IEEE
2019-01-01
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| Series: | IEEE Photonics Journal |
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| Online Access: | https://ieeexplore.ieee.org/document/8782643/ |
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| author | Mitsuo Fukuda Ryo Watanabe Yuta Tonooka Masashi Ota |
| author_facet | Mitsuo Fukuda Ryo Watanabe Yuta Tonooka Masashi Ota |
| author_sort | Mitsuo Fukuda |
| collection | DOAJ |
| description | The concept and configuration of a plasmonic cascadable full adder are proposed, whose logic operation is carried out by interference of surface plasmons and whose circuits are formed only with single- and multiple-mode plasmonic waveguides. This full adder is fabricated by patterning a SiO<sub>2</sub> film deposited on a metal film using complementary metal-oxide-semiconductor-compatible processes except for the material of metal. The redundant surface plasmons present after interference are drained from the waveguides by forming radiation ports, and metal bumps are formed in the circuits to prevent stray light recoupling with the waveguides. The logic operation of the circuits is numerically confirmed by the three-dimensional finite-difference time domain method, and the difference in surface plasmon intensity between logic level “0” and “1” is numerically estimated to be 1.5 dB even for the worst case. These simulations were experimentally confirmed for some input signal patterns using scanning near-field microscopy, and the surface plasmon intensity distributions monitored coincide well with those simulated. |
| format | Article |
| id | doaj-art-9ce05a0db2d54d77b2b822028425a6d7 |
| institution | DOAJ |
| issn | 1943-0655 |
| language | English |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Photonics Journal |
| spelling | doaj-art-9ce05a0db2d54d77b2b822028425a6d72025-08-20T03:15:48ZengIEEEIEEE Photonics Journal1943-06552019-01-0111411210.1109/JPHOT.2019.29322628782643Feasibility of Cascadable Plasmonic Full AdderMitsuo Fukuda0https://orcid.org/0000-0002-1458-281XRyo Watanabe1Yuta Tonooka2Masashi Ota3Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, JapanDepartment of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, JapanDepartment of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, JapanDepartment of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Toyohashi, JapanThe concept and configuration of a plasmonic cascadable full adder are proposed, whose logic operation is carried out by interference of surface plasmons and whose circuits are formed only with single- and multiple-mode plasmonic waveguides. This full adder is fabricated by patterning a SiO<sub>2</sub> film deposited on a metal film using complementary metal-oxide-semiconductor-compatible processes except for the material of metal. The redundant surface plasmons present after interference are drained from the waveguides by forming radiation ports, and metal bumps are formed in the circuits to prevent stray light recoupling with the waveguides. The logic operation of the circuits is numerically confirmed by the three-dimensional finite-difference time domain method, and the difference in surface plasmon intensity between logic level “0” and “1” is numerically estimated to be 1.5 dB even for the worst case. These simulations were experimentally confirmed for some input signal patterns using scanning near-field microscopy, and the surface plasmon intensity distributions monitored coincide well with those simulated.https://ieeexplore.ieee.org/document/8782643/Surface plasmon polaritonlogic circuitplasmonic waveguidefull adder. |
| spellingShingle | Mitsuo Fukuda Ryo Watanabe Yuta Tonooka Masashi Ota Feasibility of Cascadable Plasmonic Full Adder IEEE Photonics Journal Surface plasmon polariton logic circuit plasmonic waveguide full adder. |
| title | Feasibility of Cascadable Plasmonic Full Adder |
| title_full | Feasibility of Cascadable Plasmonic Full Adder |
| title_fullStr | Feasibility of Cascadable Plasmonic Full Adder |
| title_full_unstemmed | Feasibility of Cascadable Plasmonic Full Adder |
| title_short | Feasibility of Cascadable Plasmonic Full Adder |
| title_sort | feasibility of cascadable plasmonic full adder |
| topic | Surface plasmon polariton logic circuit plasmonic waveguide full adder. |
| url | https://ieeexplore.ieee.org/document/8782643/ |
| work_keys_str_mv | AT mitsuofukuda feasibilityofcascadableplasmonicfulladder AT ryowatanabe feasibilityofcascadableplasmonicfulladder AT yutatonooka feasibilityofcascadableplasmonicfulladder AT masashiota feasibilityofcascadableplasmonicfulladder |