A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS
This work presents a <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel...
Saved in:
Main Authors: | Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2025-01-01
|
Series: | IEEE Open Journal of the Solid-State Circuits Society |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/10807254/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Timing-Skew Calibration Techniques in Time-Interleaved ADCs
by: Mingyang Gu, et al.
Published: (2025-01-01) -
SAR-Assisted Energy-Efficient Hybrid ADCs
by: Kent Edrian Lozada, et al.
Published: (2024-01-01) -
Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers
by: Seoyoung Jang, et al.
Published: (2024-01-01) -
Combat effectiveness analysis model of naval gun based on combat effect
by: WANG Zhensi, YANG Shujian, HAN Hongbo
Published: (2025-02-01) -
Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology
by: Anil Singh, et al.
Published: (2017-11-01)