A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS
This work presents a <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel...
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| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10807254/ |
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| author | Lucas Moura Santana Ewout Martens Jorge Lagos Piet Wambacq Jan Craninckx |
| author_facet | Lucas Moura Santana Ewout Martens Jorge Lagos Piet Wambacq Jan Craninckx |
| author_sort | Lucas Moura Santana |
| collection | DOAJ |
| description | This work presents a <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW. |
| format | Article |
| id | doaj-art-9ab5f7e02f954c0cac35bf6b3a6bdd41 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-9ab5f7e02f954c0cac35bf6b3a6bdd412025-01-24T00:02:20ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492025-01-015112010.1109/OJSSCS.2024.352052510807254A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOSLucas Moura Santana0https://orcid.org/0000-0002-1642-2465Ewout Martens1https://orcid.org/0000-0001-5485-1837Jorge Lagos2https://orcid.org/0000-0001-5682-8737Piet Wambacq3https://orcid.org/0000-0003-4388-7257Jan Craninckx4https://orcid.org/0000-0002-3980-0203Advanced RF, imec, Leuven, BelgiumAdvanced RF, imec, Leuven, BelgiumAdvanced RF, imec, Leuven, BelgiumAdvanced RF, imec, Leuven, BelgiumAdvanced RF, imec, Leuven, BelgiumThis work presents a <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.https://ieeexplore.ieee.org/document/10807254/Cascade-of-integrators with feedforward (CIFF)delta-sigma modulationdiscrete-time (DT) analog-to-digital converter (ADC)oversampling ADCring amplification |
| spellingShingle | Lucas Moura Santana Ewout Martens Jorge Lagos Piet Wambacq Jan Craninckx A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS IEEE Open Journal of the Solid-State Circuits Society Cascade-of-integrators with feedforward (CIFF) delta-sigma modulation discrete-time (DT) analog-to-digital converter (ADC) oversampling ADC ring amplification |
| title | A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS |
| title_full | A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS |
| title_fullStr | A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS |
| title_full_unstemmed | A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS |
| title_short | A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS |
| title_sort | 70 mhz bandwidth time interleaved noise shaping sar assisted delta sigma adc with digital cross coupling in 28 nm cmos |
| topic | Cascade-of-integrators with feedforward (CIFF) delta-sigma modulation discrete-time (DT) analog-to-digital converter (ADC) oversampling ADC ring amplification |
| url | https://ieeexplore.ieee.org/document/10807254/ |
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