Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies
With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, which requires robust protection mechanisms for sensitive data and critical infrastructure. The...
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| Format: | Article |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10852325/ |
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| author | Salman Ahmed Nabihah Ahmad Nasir Ali Shah Ghulam E. Mustafa Abro Ardhi Wijayanto Abdinasir Hirsi Abdul Rehman Altaf |
| author_facet | Salman Ahmed Nabihah Ahmad Nasir Ali Shah Ghulam E. Mustafa Abro Ardhi Wijayanto Abdinasir Hirsi Abdul Rehman Altaf |
| author_sort | Salman Ahmed |
| collection | DOAJ |
| description | With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, which requires robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). In addition, the analysis explores fault scenarios, rounds, and injection positions to assess the severity of the fault. In addition, the study reviews DFA countermeasures that highlight fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments. |
| format | Article |
| id | doaj-art-9a84329ac2b64a41a212d21f10d84194 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-9a84329ac2b64a41a212d21f10d841942025-02-07T00:01:09ZengIEEEIEEE Access2169-35362025-01-0113224892250910.1109/ACCESS.2025.353361110852325Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure StrategiesSalman Ahmed0https://orcid.org/0009-0003-7129-7892Nabihah Ahmad1https://orcid.org/0000-0003-0989-7021Nasir Ali Shah2https://orcid.org/0000-0003-2276-4960Ghulam E. Mustafa Abro3https://orcid.org/0000-0003-1874-1889Ardhi Wijayanto4https://orcid.org/0000-0001-6187-0593Abdinasir Hirsi5https://orcid.org/0000-0001-8543-6134Abdul Rehman Altaf6https://orcid.org/0000-0003-0653-5113Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, MalaysiaFaculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, MalaysiaDepartment of Electronics and Telecommunication (DET), Politecnico di Torino, Turin, ItalyInterdisciplinary Research Centre for Aviation and Space Exploration (IRC-ASE), King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi ArabiaFaculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, MalaysiaFaculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, MalaysiaJohns Hopkins Aramco Healthcare (JHAH), Dhahran, Saudi ArabiaWith the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, which requires robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). In addition, the analysis explores fault scenarios, rounds, and injection positions to assess the severity of the fault. In addition, the study reviews DFA countermeasures that highlight fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments.https://ieeexplore.ieee.org/document/10852325/Advanced encryption standard (AES)application specific integrated circuits (ASIC)differential fault analysis (DFA)field programmable gate arrays (FPGA)Galois field (GF)Internet of Things (IoT) |
| spellingShingle | Salman Ahmed Nabihah Ahmad Nasir Ali Shah Ghulam E. Mustafa Abro Ardhi Wijayanto Abdinasir Hirsi Abdul Rehman Altaf Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies IEEE Access Advanced encryption standard (AES) application specific integrated circuits (ASIC) differential fault analysis (DFA) field programmable gate arrays (FPGA) Galois field (GF) Internet of Things (IoT) |
| title | Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies |
| title_full | Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies |
| title_fullStr | Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies |
| title_full_unstemmed | Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies |
| title_short | Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies |
| title_sort | lightweight aes design for iot applications optimizations in fpga and asic with dfa countermeasure strategies |
| topic | Advanced encryption standard (AES) application specific integrated circuits (ASIC) differential fault analysis (DFA) field programmable gate arrays (FPGA) Galois field (GF) Internet of Things (IoT) |
| url | https://ieeexplore.ieee.org/document/10852325/ |
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