A Novel 3D Mesh-Based NoC Architecture for Performance Improvement
Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption and latency compared with two-dimensional (2D...
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| Format: | Article |
| Language: | English |
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OICC Press
2022-06-01
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| Series: | Majlesi Journal of Electrical Engineering |
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| Online Access: | https://oiccpress.com/mjee/article/view/4953 |
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| author | Navid Habibi MohammadReza Salehnamadi Ahmad Khademzadeh |
| author_facet | Navid Habibi MohammadReza Salehnamadi Ahmad Khademzadeh |
| author_sort | Navid Habibi |
| collection | DOAJ |
| description | Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption and latency compared with two-dimensional (2D) ones. Recently developed architectures are based on regular mesh. However, there are serious drawbacks in NoC architectures including high power consumption, energy consumption, and latency. Therefore, making an improvement in topology diameter would overcome these shortcomings. Accordingly, a new 3D mesh-based NoC architecture is proposed in the present study utilizing the star node, consisting of a new 3D topology with small diameter and new deadlock-free routing. The diameter of this architecture is then compared with its counterparts. Afterwards, the scalable universal matrix multiplication algorithm (SUMMA) is implemented in the proposed architecture. The results indicate a smaller network diameter, lower energy consumption (32%), less network latency (8.6%), as well as enhancement in throughput average (13.6%). The proposed matrix multiplication algorithm also implies improvement in the cost of the proposed architecture in comparison with its counterparts. |
| format | Article |
| id | doaj-art-962cd5656eaf404bbb4d9e71d9d5cb6d |
| institution | DOAJ |
| issn | 2345-377X 2345-3796 |
| language | English |
| publishDate | 2022-06-01 |
| publisher | OICC Press |
| record_format | Article |
| series | Majlesi Journal of Electrical Engineering |
| spelling | doaj-art-962cd5656eaf404bbb4d9e71d9d5cb6d2025-08-20T03:04:17ZengOICC PressMajlesi Journal of Electrical Engineering2345-377X2345-37962022-06-0116210.30486/mjee.2022.696497A Novel 3D Mesh-Based NoC Architecture for Performance ImprovementNavid Habibi0MohammadReza Salehnamadi1Ahmad Khademzadeh2Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran) Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, IranTelecommunication Research Center, Tehran, IranApplying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption and latency compared with two-dimensional (2D) ones. Recently developed architectures are based on regular mesh. However, there are serious drawbacks in NoC architectures including high power consumption, energy consumption, and latency. Therefore, making an improvement in topology diameter would overcome these shortcomings. Accordingly, a new 3D mesh-based NoC architecture is proposed in the present study utilizing the star node, consisting of a new 3D topology with small diameter and new deadlock-free routing. The diameter of this architecture is then compared with its counterparts. Afterwards, the scalable universal matrix multiplication algorithm (SUMMA) is implemented in the proposed architecture. The results indicate a smaller network diameter, lower energy consumption (32%), less network latency (8.6%), as well as enhancement in throughput average (13.6%). The proposed matrix multiplication algorithm also implies improvement in the cost of the proposed architecture in comparison with its counterparts.https://oiccpress.com/mjee/article/view/4953CommunicationNetwork-on-Chipnetworks ArchitecturePerformance EvaluationSystem-on-chip. Routing ProtocolsTopology |
| spellingShingle | Navid Habibi MohammadReza Salehnamadi Ahmad Khademzadeh A Novel 3D Mesh-Based NoC Architecture for Performance Improvement Majlesi Journal of Electrical Engineering Communication Network-on-Chip networks Architecture Performance Evaluation System-on-chip. Routing Protocols Topology |
| title | A Novel 3D Mesh-Based NoC Architecture for Performance Improvement |
| title_full | A Novel 3D Mesh-Based NoC Architecture for Performance Improvement |
| title_fullStr | A Novel 3D Mesh-Based NoC Architecture for Performance Improvement |
| title_full_unstemmed | A Novel 3D Mesh-Based NoC Architecture for Performance Improvement |
| title_short | A Novel 3D Mesh-Based NoC Architecture for Performance Improvement |
| title_sort | novel 3d mesh based noc architecture for performance improvement |
| topic | Communication Network-on-Chip networks Architecture Performance Evaluation System-on-chip. Routing Protocols Topology |
| url | https://oiccpress.com/mjee/article/view/4953 |
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