Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain
In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short pa...
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2014/546264 |
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| _version_ | 1850208471962615808 |
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| author | Guillermo A. Jaquenod Javier Valls Javier Siman |
| author_facet | Guillermo A. Jaquenod Javier Valls Javier Siman |
| author_sort | Guillermo A. Jaquenod |
| collection | DOAJ |
| description | In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel. |
| format | Article |
| id | doaj-art-961795491faa40568bd8aafa1d2e0b84 |
| institution | OA Journals |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-961795491faa40568bd8aafa1d2e0b842025-08-20T02:10:14ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092014-01-01201410.1155/2014/546264546264Efficient FPGA Hardware Reuse in a Multiplierless Decimation ChainGuillermo A. Jaquenod0Javier Valls1Javier Siman2Facultad de Ingeniería, Universidad Nacional del Centro, 7400 Olavarría, ArgentinaInstituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, 46730 Gandia, SpainDTA S.A., 5000 Córdoba, ArgentinaIn digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.http://dx.doi.org/10.1155/2014/546264 |
| spellingShingle | Guillermo A. Jaquenod Javier Valls Javier Siman Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain International Journal of Reconfigurable Computing |
| title | Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain |
| title_full | Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain |
| title_fullStr | Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain |
| title_full_unstemmed | Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain |
| title_short | Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain |
| title_sort | efficient fpga hardware reuse in a multiplierless decimation chain |
| url | http://dx.doi.org/10.1155/2014/546264 |
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