Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter

Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter

In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work...

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Bibliographic Details
Main Authors: Bin Wang, Ziyuan Tang, Yuxiang Song, Lu Liu, Weitao Yang, Longsheng Wu
Format: Article
Language:English
Published: MDPI AG 2025-01-01
Series:Micromachines
Subjects:
PD-SOI
junctionless FET
buried layer
CMOS inverter
Online Access:https://www.mdpi.com/2072-666X/16/1/106
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