Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter
In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-01-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/16/1/106 |
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| Summary: | In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an I<sub>on</sub>/I<sub>off</sub> ratio of more than seven orders of magnitude, with I<sub>on</sub> reaching up to 2.56 × 10<sup>−4</sup> A/μm, I<sub>off</sub> as low as 3.99 × 10<sup>−12</sup> A/μm, and a threshold voltage reduced to −0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future. |
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| ISSN: | 2072-666X |