Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs
This paper presents two novel digital-to-analog converter (DAC) designs that leverage the split capacitor approach. The designs optimize speed, and accuracy, significantly improving linearity and overall performance. Integrating a binary-to-thermometer code (B-TC) decoder at the switching network of...
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| Format: | Article |
| Language: | English |
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EDP Sciences
2025-01-01
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| Series: | ITM Web of Conferences |
| Online Access: | https://www.itm-conferences.org/articles/itmconf/pdf/2025/05/itmconf_iccp-ci2024_02009.pdf |
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| _version_ | 1849705503534350336 |
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| author | Bandla Kasi Iqubal Asif Pal Dipankar |
| author_facet | Bandla Kasi Iqubal Asif Pal Dipankar |
| author_sort | Bandla Kasi |
| collection | DOAJ |
| description | This paper presents two novel digital-to-analog converter (DAC) designs that leverage the split capacitor approach. The designs optimize speed, and accuracy, significantly improving linearity and overall performance. Integrating a binary-to-thermometer code (B-TC) decoder at the switching network of the split capacitor techniques further enhances the performance of DACs in terms of linearity, and speed. Also, it reduces the capacitive mismatch associated with capacitive DAC designs. Using Cadence Virtuoso UMC 180nm technology, the designs were implemented with a 90fF capacitance value at 1.8V supply voltage. The performance of these proposed DAC configurations, one with a B-TC decoder and another without is assessed through simulation to benchmark them against state-of-the art designs. According to simulation results, the DAC with an integrated B-TC decoder performs significantly better, which makes it ideal for SAR-ADC design applications that need high speed, low power consumption, and area efficiency. |
| format | Article |
| id | doaj-art-9255f7fdf0384ff98ad97171c1f7da2b |
| institution | DOAJ |
| issn | 2271-2097 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | EDP Sciences |
| record_format | Article |
| series | ITM Web of Conferences |
| spelling | doaj-art-9255f7fdf0384ff98ad97171c1f7da2b2025-08-20T03:16:28ZengEDP SciencesITM Web of Conferences2271-20972025-01-01740200910.1051/itmconf/20257402009itmconf_iccp-ci2024_02009Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCsBandla Kasi0Iqubal Asif1Pal Dipankar2Dept. of ECE, Sreenidhi Institute of Science and TechnologyDept. of EEE, BITS-Pilani, K K Birla Goa CampusDept. of EEE, BITS-Pilani, K K Birla Goa CampusThis paper presents two novel digital-to-analog converter (DAC) designs that leverage the split capacitor approach. The designs optimize speed, and accuracy, significantly improving linearity and overall performance. Integrating a binary-to-thermometer code (B-TC) decoder at the switching network of the split capacitor techniques further enhances the performance of DACs in terms of linearity, and speed. Also, it reduces the capacitive mismatch associated with capacitive DAC designs. Using Cadence Virtuoso UMC 180nm technology, the designs were implemented with a 90fF capacitance value at 1.8V supply voltage. The performance of these proposed DAC configurations, one with a B-TC decoder and another without is assessed through simulation to benchmark them against state-of-the art designs. According to simulation results, the DAC with an integrated B-TC decoder performs significantly better, which makes it ideal for SAR-ADC design applications that need high speed, low power consumption, and area efficiency.https://www.itm-conferences.org/articles/itmconf/pdf/2025/05/itmconf_iccp-ci2024_02009.pdf |
| spellingShingle | Bandla Kasi Iqubal Asif Pal Dipankar Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs ITM Web of Conferences |
| title | Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs |
| title_full | Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs |
| title_fullStr | Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs |
| title_full_unstemmed | Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs |
| title_short | Design and Performance Optimization of Split Capacitor Digital-to-Analog Converter(DAC) for SAR-ADCs |
| title_sort | design and performance optimization of split capacitor digital to analog converter dac for sar adcs |
| url | https://www.itm-conferences.org/articles/itmconf/pdf/2025/05/itmconf_iccp-ci2024_02009.pdf |
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