Design of Approximate Adder With Reconfigurable Accuracy
Arithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper pr...
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2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/10847823/ |
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| author | Aalelai Vendhan Syed Ershad Ahmed S. Gurunarayanan |
| author_facet | Aalelai Vendhan Syed Ershad Ahmed S. Gurunarayanan |
| author_sort | Aalelai Vendhan |
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| description | Arithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper proposes a segmentation technique to design ternary approximate adders, where the entire adder chain is split into segments, with the intent to reduce the delay. Next, for applications that require tunable accuracy, we incorporate a reconfiguration technique in the segmented approximate adders, using a divide-and-conquer methodology that dynamically optimizes the approximate adder’s accuracy, leading to efficient computation. Also, an algorithm was proposed to compute accuracy and hardware complexity in an N-trit accuracy reconfigurable adder. The proposed methodology was validated using an approximate 6-trit adder on its power consumption and delay performance metrics. Compared with the best design in literature, the proposed approximate 6-trit adder exhibits 63% lesser power consumption and 69% lesser delay. The proposed approximate 6-trit adder accuracy was progressively enhanced through the reconfigurable method. After a few reconfiguration stages, the proposed adder matched the accuracy of an exact 6-trit adder while achieving an improved power-delay product (PDP). Finally, the proposed 6-trit adders were validated by using them in the image-blending application. |
| format | Article |
| id | doaj-art-9219a2eb0aa849a68bd29144b0a91e73 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-9219a2eb0aa849a68bd29144b0a91e732025-01-31T00:01:02ZengIEEEIEEE Access2169-35362025-01-0113170301704210.1109/ACCESS.2025.353194310847823Design of Approximate Adder With Reconfigurable AccuracyAalelai Vendhan0https://orcid.org/0000-0002-0366-9522Syed Ershad Ahmed1https://orcid.org/0000-0003-0333-9387S. Gurunarayanan2https://orcid.org/0000-0001-5596-4964Electrical and Electronics Engineering Department, BITS Pilani, Hyderabad Campus, Hyderabad, IndiaElectrical and Electronics Engineering Department, BITS Pilani, Hyderabad Campus, Hyderabad, IndiaElectrical and Electronics Engineering Department, BITS Pilani, Hyderabad Campus, Hyderabad, IndiaArithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining accuracy within tolerance limits. This paper proposes a segmentation technique to design ternary approximate adders, where the entire adder chain is split into segments, with the intent to reduce the delay. Next, for applications that require tunable accuracy, we incorporate a reconfiguration technique in the segmented approximate adders, using a divide-and-conquer methodology that dynamically optimizes the approximate adder’s accuracy, leading to efficient computation. Also, an algorithm was proposed to compute accuracy and hardware complexity in an N-trit accuracy reconfigurable adder. The proposed methodology was validated using an approximate 6-trit adder on its power consumption and delay performance metrics. Compared with the best design in literature, the proposed approximate 6-trit adder exhibits 63% lesser power consumption and 69% lesser delay. The proposed approximate 6-trit adder accuracy was progressively enhanced through the reconfigurable method. After a few reconfiguration stages, the proposed adder matched the accuracy of an exact 6-trit adder while achieving an improved power-delay product (PDP). Finally, the proposed 6-trit adders were validated by using them in the image-blending application.https://ieeexplore.ieee.org/document/10847823/Accuracy reconfigurationimage processingternary logicapproximate computing |
| spellingShingle | Aalelai Vendhan Syed Ershad Ahmed S. Gurunarayanan Design of Approximate Adder With Reconfigurable Accuracy IEEE Access Accuracy reconfiguration image processing ternary logic approximate computing |
| title | Design of Approximate Adder With Reconfigurable Accuracy |
| title_full | Design of Approximate Adder With Reconfigurable Accuracy |
| title_fullStr | Design of Approximate Adder With Reconfigurable Accuracy |
| title_full_unstemmed | Design of Approximate Adder With Reconfigurable Accuracy |
| title_short | Design of Approximate Adder With Reconfigurable Accuracy |
| title_sort | design of approximate adder with reconfigurable accuracy |
| topic | Accuracy reconfiguration image processing ternary logic approximate computing |
| url | https://ieeexplore.ieee.org/document/10847823/ |
| work_keys_str_mv | AT aalelaivendhan designofapproximateadderwithreconfigurableaccuracy AT syedershadahmed designofapproximateadderwithreconfigurableaccuracy AT sgurunarayanan designofapproximateadderwithreconfigurableaccuracy |