High-Level Synthesis under Fixed-Point Accuracy Constraint
Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/906350 |
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| author | Daniel Menard Nicolas Herve Olivier Sentieys Hai-Nam Nguyen |
| author_facet | Daniel Menard Nicolas Herve Olivier Sentieys Hai-Nam Nguyen |
| author_sort | Daniel Menard |
| collection | DOAJ |
| description | Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%. |
| format | Article |
| id | doaj-art-91f8e48d79ce49ee963e1bb4fe001828 |
| institution | OA Journals |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-91f8e48d79ce49ee963e1bb4fe0018282025-08-20T02:10:02ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/906350906350High-Level Synthesis under Fixed-Point Accuracy ConstraintDaniel Menard0Nicolas Herve1Olivier Sentieys2Hai-Nam Nguyen3IRISA/ENSSAT, University of Rennes, 6 rue de Kerampont, 22305 Lannion, FranceIRISA/ENSSAT, University of Rennes, 6 rue de Kerampont, 22305 Lannion, FranceIRISA/ENSSAT, University of Rennes, 6 rue de Kerampont, 22305 Lannion, FranceIRISA/ENSSAT, University of Rennes, 6 rue de Kerampont, 22305 Lannion, FranceImplementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.http://dx.doi.org/10.1155/2012/906350 |
| spellingShingle | Daniel Menard Nicolas Herve Olivier Sentieys Hai-Nam Nguyen High-Level Synthesis under Fixed-Point Accuracy Constraint Journal of Electrical and Computer Engineering |
| title | High-Level Synthesis under Fixed-Point Accuracy Constraint |
| title_full | High-Level Synthesis under Fixed-Point Accuracy Constraint |
| title_fullStr | High-Level Synthesis under Fixed-Point Accuracy Constraint |
| title_full_unstemmed | High-Level Synthesis under Fixed-Point Accuracy Constraint |
| title_short | High-Level Synthesis under Fixed-Point Accuracy Constraint |
| title_sort | high level synthesis under fixed point accuracy constraint |
| url | http://dx.doi.org/10.1155/2012/906350 |
| work_keys_str_mv | AT danielmenard highlevelsynthesisunderfixedpointaccuracyconstraint AT nicolasherve highlevelsynthesisunderfixedpointaccuracyconstraint AT oliviersentieys highlevelsynthesisunderfixedpointaccuracyconstraint AT hainamnguyen highlevelsynthesisunderfixedpointaccuracyconstraint |