Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA
Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timin...
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| Format: | Article |
| Language: | English |
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Sakarya University
2021-12-01
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| Series: | Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi |
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| Online Access: | https://dergipark.org.tr/tr/download/article-file/1566861 |
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| _version_ | 1850134583050240000 |
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| author | Dursun Baran |
| author_facet | Dursun Baran |
| author_sort | Dursun Baran |
| collection | DOAJ |
| description | Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided. |
| format | Article |
| id | doaj-art-8fa46e5865444d8aad8d92af6fd494ab |
| institution | OA Journals |
| issn | 2147-835X |
| language | English |
| publishDate | 2021-12-01 |
| publisher | Sakarya University |
| record_format | Article |
| series | Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi |
| spelling | doaj-art-8fa46e5865444d8aad8d92af6fd494ab2025-08-20T02:31:40ZengSakarya UniversitySakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi2147-835X2021-12-012561386139310.16984/saufenbilder.87745328Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGADursun Baran0https://orcid.org/0000-0001-9277-3796TÜRKİYE BİLİMSEL ve TEKNOLOJİK ARAŞTIRMA KURUMUResource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.https://dergipark.org.tr/tr/download/article-file/1566861parallel fft corereal time spectrum analysisenergy-efficient designfpga |
| spellingShingle | Dursun Baran Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi parallel fft core real time spectrum analysis energy-efficient design fpga |
| title | Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA |
| title_full | Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA |
| title_fullStr | Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA |
| title_full_unstemmed | Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA |
| title_short | Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA |
| title_sort | reconfigurable and resource efficient implementation of a parallel fft core in fpga |
| topic | parallel fft core real time spectrum analysis energy-efficient design fpga |
| url | https://dergipark.org.tr/tr/download/article-file/1566861 |
| work_keys_str_mv | AT dursunbaran reconfigurableandresourceefficientimplementationofaparallelfftcoreinfpga |