Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timin...

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Bibliographic Details
Main Author: Dursun Baran
Format: Article
Language:English
Published: Sakarya University 2021-12-01
Series:Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi
Subjects:
parallel fft core
real time spectrum analysis
energy-efficient design
fpga
Online Access:https://dergipark.org.tr/tr/download/article-file/1566861
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Summary:Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.
ISSN:2147-835X

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