An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier
Information is deteriorated by communication channels in several ways. The most notable is the addition of noise to the signal during transmission. Noise is reduced by the use of adaptive filters. Wiener, Steepest, and LMS are the most often utilized. While in hardware translation on ASICS and FPGAs...
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| Format: | Article |
| Language: | English |
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Mehran University of Engineering and Technology
2025-04-01
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| Series: | Mehran University Research Journal of Engineering and Technology |
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| Online Access: | https://murjet.muet.edu.pk/index.php/home/article/view/295 |
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| author | Aneela Pathan Khalil M. Zohaib Rizwan Aziz Adil Hussain Chandio Syed Haseeb Shah |
| author_facet | Aneela Pathan Khalil M. Zohaib Rizwan Aziz Adil Hussain Chandio Syed Haseeb Shah |
| author_sort | Aneela Pathan |
| collection | DOAJ |
| description | Information is deteriorated by communication channels in several ways. The most notable is the addition of noise to the signal during transmission. Noise is reduced by the use of adaptive filters. Wiener, Steepest, and LMS are the most often utilized. While in hardware translation on ASICS and FPGAs, adaptive filters require more resources than straightforward FIR or IIR designs. Reducing resources is necessary to optimize the implementation. The literature on resource-optimized filter implementation with multiplier optimization has been seen with a number of approaches. In this study, a new proposed shift and add multiplier is used to create an FPGA-based adaptive noise canceller based on the Steepest -descent algorithm, and its performance is compared with a traditional version. The adaptive noise canceller is first simulated in MATLAB and then designed in Xilinx Virtex 7 FPGA using the ISE 14.7 tool, but the proposed architecture is too flexible to be carried out on any FPGA board. The suggested shift and add multiplier consume less FPGA resources than the original shift and add multiplication scheme alone, and in designing an adaptive noise canceller. The proposed method also performs better than the conventional approach in terms of maximum frequency achieved. Therefore, it can be inferred that the proposed shift and add multiplier approach can be adapted for resource-optimized implementation in the communication domain and in DSP applications. |
| format | Article |
| id | doaj-art-8ea01b454fe94231a28617978701c6a4 |
| institution | DOAJ |
| issn | 0254-7821 2413-7219 |
| language | English |
| publishDate | 2025-04-01 |
| publisher | Mehran University of Engineering and Technology |
| record_format | Article |
| series | Mehran University Research Journal of Engineering and Technology |
| spelling | doaj-art-8ea01b454fe94231a28617978701c6a42025-08-20T03:06:06ZengMehran University of Engineering and TechnologyMehran University Research Journal of Engineering and Technology0254-78212413-72192025-04-0144213614310.22581/muet1982.3220297An optimized implementation of adaptive noise canceller based on proposed shift and add multiplierAneela Pathan0Khalil M. Zohaib1Rizwan Aziz2Adil Hussain Chandio3Syed Haseeb Shah4Department of Electronic Engineering, The University of Larkana, Larkana, PakistanDepartment of Electronic Engineering, The University of Larkana, Larkana, PakistanDepartment of Electronic Engineering, The University of Larkana, Larkana, PakistanDepartment of Electronic Engineering, The University of Larkana, Larkana, PakistanDepartment of Electronic Engineering, The University of Larkana, Larkana, PakistanInformation is deteriorated by communication channels in several ways. The most notable is the addition of noise to the signal during transmission. Noise is reduced by the use of adaptive filters. Wiener, Steepest, and LMS are the most often utilized. While in hardware translation on ASICS and FPGAs, adaptive filters require more resources than straightforward FIR or IIR designs. Reducing resources is necessary to optimize the implementation. The literature on resource-optimized filter implementation with multiplier optimization has been seen with a number of approaches. In this study, a new proposed shift and add multiplier is used to create an FPGA-based adaptive noise canceller based on the Steepest -descent algorithm, and its performance is compared with a traditional version. The adaptive noise canceller is first simulated in MATLAB and then designed in Xilinx Virtex 7 FPGA using the ISE 14.7 tool, but the proposed architecture is too flexible to be carried out on any FPGA board. The suggested shift and add multiplier consume less FPGA resources than the original shift and add multiplication scheme alone, and in designing an adaptive noise canceller. The proposed method also performs better than the conventional approach in terms of maximum frequency achieved. Therefore, it can be inferred that the proposed shift and add multiplier approach can be adapted for resource-optimized implementation in the communication domain and in DSP applications.https://murjet.muet.edu.pk/index.php/home/article/view/295dspfpgamatlabshift and addoptimization |
| spellingShingle | Aneela Pathan Khalil M. Zohaib Rizwan Aziz Adil Hussain Chandio Syed Haseeb Shah An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier Mehran University Research Journal of Engineering and Technology dsp fpga matlab shift and add optimization |
| title | An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| title_full | An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| title_fullStr | An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| title_full_unstemmed | An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| title_short | An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| title_sort | optimized implementation of adaptive noise canceller based on proposed shift and add multiplier |
| topic | dsp fpga matlab shift and add optimization |
| url | https://murjet.muet.edu.pk/index.php/home/article/view/295 |
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