SOT-MRAM-based true in-memory computing architecture for approximate multiplication
The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was pres...
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Elsevier
2025-06-01
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| Series: | Chip |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2709472325000085 |
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| author | Min Song Qilong Tang Xintong Ouyang Wei Duan Yan Xu Shuai Zhang Long You |
| author_facet | Min Song Qilong Tang Xintong Ouyang Wei Duan Yan Xu Shuai Zhang Long You |
| author_sort | Min Song |
| collection | DOAJ |
| description | The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was presented, where computations were performed natively within the cell array instead of in peripheral circuits. Firstly, basic Boolean logic operations were realized by utilizing the feature of unipolar SOT device. Two majority gate-based imprecise compressors and an ultra-efficient approximate multiplier were then built to reduce the energy and latency. An optimized data mapping strategy facilitating bit-serial operations with an extensive degree of parallelism was also adopted. Finally, the performance enhancements by performing our approximate multiplier in image smoothing were demonstrated. Detailed simulation results show that the proposed 8 × 8 approximate multiplier could reduce the energy and latency at least by 74.2% and 44.4% compared with the existing designs. Moreover, the scheme could achieve improved peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM), ensuring high-quality image processing outcomes. |
| format | Article |
| id | doaj-art-8d0366d070f74a31b95d8729e259d312 |
| institution | OA Journals |
| issn | 2709-4723 |
| language | English |
| publishDate | 2025-06-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Chip |
| spelling | doaj-art-8d0366d070f74a31b95d8729e259d3122025-08-20T02:26:09ZengElsevierChip2709-47232025-06-014210013410.1016/j.chip.2025.100134SOT-MRAM-based true in-memory computing architecture for approximate multiplicationMin Song0Qilong Tang1Xintong Ouyang2Wei Duan3Yan Xu4Shuai Zhang5Long You6Key Laboratory of Intelligent Sensing System and Security of the Ministry of Education, Hubei Key Laboratory of Micro-Nanoelectronic Materials and Devices, School of Microelectronics, Hubei University, Wuhan 430062, ChinaKey Laboratory of Intelligent Sensing System and Security of the Ministry of Education, Hubei Key Laboratory of Micro-Nanoelectronic Materials and Devices, School of Microelectronics, Hubei University, Wuhan 430062, ChinaKey Laboratory of Intelligent Sensing System and Security of the Ministry of Education, Hubei Key Laboratory of Micro-Nanoelectronic Materials and Devices, School of Microelectronics, Hubei University, Wuhan 430062, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China; Corresponding author.The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was presented, where computations were performed natively within the cell array instead of in peripheral circuits. Firstly, basic Boolean logic operations were realized by utilizing the feature of unipolar SOT device. Two majority gate-based imprecise compressors and an ultra-efficient approximate multiplier were then built to reduce the energy and latency. An optimized data mapping strategy facilitating bit-serial operations with an extensive degree of parallelism was also adopted. Finally, the performance enhancements by performing our approximate multiplier in image smoothing were demonstrated. Detailed simulation results show that the proposed 8 × 8 approximate multiplier could reduce the energy and latency at least by 74.2% and 44.4% compared with the existing designs. Moreover, the scheme could achieve improved peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM), ensuring high-quality image processing outcomes.http://www.sciencedirect.com/science/article/pii/S2709472325000085Spin-orbit torque (SOT)Magnetoresistive random access memory (MRAM)In-memory computing (IMC)Approximate multiplierData mapping strategy |
| spellingShingle | Min Song Qilong Tang Xintong Ouyang Wei Duan Yan Xu Shuai Zhang Long You SOT-MRAM-based true in-memory computing architecture for approximate multiplication Chip Spin-orbit torque (SOT) Magnetoresistive random access memory (MRAM) In-memory computing (IMC) Approximate multiplier Data mapping strategy |
| title | SOT-MRAM-based true in-memory computing architecture for approximate multiplication |
| title_full | SOT-MRAM-based true in-memory computing architecture for approximate multiplication |
| title_fullStr | SOT-MRAM-based true in-memory computing architecture for approximate multiplication |
| title_full_unstemmed | SOT-MRAM-based true in-memory computing architecture for approximate multiplication |
| title_short | SOT-MRAM-based true in-memory computing architecture for approximate multiplication |
| title_sort | sot mram based true in memory computing architecture for approximate multiplication |
| topic | Spin-orbit torque (SOT) Magnetoresistive random access memory (MRAM) In-memory computing (IMC) Approximate multiplier Data mapping strategy |
| url | http://www.sciencedirect.com/science/article/pii/S2709472325000085 |
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