Power‐jitter trade‐off analysis in digital‐to‐time converters
Digital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS conver...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4577 |
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| _version_ | 1832096682545774592 |
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| author | A. Santiccioli C. Samori A.L. Lacaita S. Levantino |
| author_facet | A. Santiccioli C. Samori A.L. Lacaita S. Levantino |
| author_sort | A. Santiccioli |
| collection | DOAJ |
| description | Digital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period. |
| format | Article |
| id | doaj-art-8c8eefb51cfb4269b979fb00e5fb32a5 |
| institution | Kabale University |
| issn | 0013-5194 1350-911X |
| language | English |
| publishDate | 2017-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj-art-8c8eefb51cfb4269b979fb00e5fb32a52025-02-05T12:30:42ZengWileyElectronics Letters0013-51941350-911X2017-03-0153530630810.1049/el.2016.4577Power‐jitter trade‐off analysis in digital‐to‐time convertersA. Santiccioli0C. Samori1A.L. Lacaita2S. Levantino3Department of Electronics, Information and BioengineeringPolitecnico di MilanoMilanItalyDepartment of Electronics, Information and BioengineeringPolitecnico di MilanoMilanItalyDepartment of Electronics, Information and BioengineeringPolitecnico di MilanoMilanItalyDepartment of Electronics, Information and BioengineeringPolitecnico di MilanoMilanItalyDigital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period.https://doi.org/10.1049/el.2016.4577power‐jitter trade‐off analysisdigital‐to‐time converterstime‐domain signal processingjitter‐power productfull‐scale delay rangecurrent‐mode logic implementations |
| spellingShingle | A. Santiccioli C. Samori A.L. Lacaita S. Levantino Power‐jitter trade‐off analysis in digital‐to‐time converters Electronics Letters power‐jitter trade‐off analysis digital‐to‐time converters time‐domain signal processing jitter‐power product full‐scale delay range current‐mode logic implementations |
| title | Power‐jitter trade‐off analysis in digital‐to‐time converters |
| title_full | Power‐jitter trade‐off analysis in digital‐to‐time converters |
| title_fullStr | Power‐jitter trade‐off analysis in digital‐to‐time converters |
| title_full_unstemmed | Power‐jitter trade‐off analysis in digital‐to‐time converters |
| title_short | Power‐jitter trade‐off analysis in digital‐to‐time converters |
| title_sort | power jitter trade off analysis in digital to time converters |
| topic | power‐jitter trade‐off analysis digital‐to‐time converters time‐domain signal processing jitter‐power product full‐scale delay range current‐mode logic implementations |
| url | https://doi.org/10.1049/el.2016.4577 |
| work_keys_str_mv | AT asanticcioli powerjittertradeoffanalysisindigitaltotimeconverters AT csamori powerjittertradeoffanalysisindigitaltotimeconverters AT allacaita powerjittertradeoffanalysisindigitaltotimeconverters AT slevantino powerjittertradeoffanalysisindigitaltotimeconverters |