Signal Transition Graphs for Asynchronous Data Path Circuits
The paper proposes a method for constructing signal transition graphs (STGs), which are directly mapped into asynchronous circuits for data processing. The advantage of the proposed method is that the resulting circuits are not only output-persistent, but also conformant to the environment. In other...
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| Language: | English |
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Yaroslavl State University
2023-06-01
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| Series: | Моделирование и анализ информационных систем |
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| Online Access: | https://www.mais-journal.ru/jour/article/view/1778 |
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| author | Alex Kushnerov Sergey Bystrov |
| author_facet | Alex Kushnerov Sergey Bystrov |
| author_sort | Alex Kushnerov |
| collection | DOAJ |
| description | The paper proposes a method for constructing signal transition graphs (STGs), which are directly mapped into asynchronous circuits for data processing. The advantage of the proposed method is that the resulting circuits are not only output-persistent, but also conformant to the environment. In other approaches, the environment is specified implicitly and/or inexactly and therefore they guarantee only output persistence. The conformation can be verified if both the circuit and its environment are specified by STGs. As an example, we consider a module realizing the function AND2. This module can either wait for both 1s or evaluate the function as soon as at least one 0 arrives. For each case, we draw up a separate STG (scenario) and map it into NCL gates. To provide such a mapping, we specify the behaviors of NCL gates by STG protocols. For data path, such an STG always contains alternative branches with the so-called garbage transitions at the gate inputs. The garbage transitions on a certain wire mean that the circuit is sensitive to the delay in this wire. Ignoring the garbage may lead to a violation of conformation or/and output persistence. For example, in the combinational part of the NCL circuits, the garbage appears on the inputs of NCL gates, and therefore these circuits are not delay insensitive. |
| format | Article |
| id | doaj-art-87c07a72946c467b8f7ce30ebd1f2d56 |
| institution | DOAJ |
| issn | 1818-1015 2313-5417 |
| language | English |
| publishDate | 2023-06-01 |
| publisher | Yaroslavl State University |
| record_format | Article |
| series | Моделирование и анализ информационных систем |
| spelling | doaj-art-87c07a72946c467b8f7ce30ebd1f2d562025-08-20T03:22:04ZengYaroslavl State UniversityМоделирование и анализ информационных систем1818-10152313-54172023-06-0130217018610.18255/1818-1015-2023-2-170-1861369Signal Transition Graphs for Asynchronous Data Path CircuitsAlex Kushnerov0Sergey Bystrov1Независимый исследовательIndependent researcherThe paper proposes a method for constructing signal transition graphs (STGs), which are directly mapped into asynchronous circuits for data processing. The advantage of the proposed method is that the resulting circuits are not only output-persistent, but also conformant to the environment. In other approaches, the environment is specified implicitly and/or inexactly and therefore they guarantee only output persistence. The conformation can be verified if both the circuit and its environment are specified by STGs. As an example, we consider a module realizing the function AND2. This module can either wait for both 1s or evaluate the function as soon as at least one 0 arrives. For each case, we draw up a separate STG (scenario) and map it into NCL gates. To provide such a mapping, we specify the behaviors of NCL gates by STG protocols. For data path, such an STG always contains alternative branches with the so-called garbage transitions at the gate inputs. The garbage transitions on a certain wire mean that the circuit is sensitive to the delay in this wire. Ignoring the garbage may lead to a violation of conformation or/and output persistence. For example, in the combinational part of the NCL circuits, the garbage appears on the inputs of NCL gates, and therefore these circuits are not delay insensitive.https://www.mais-journal.ru/jour/article/view/1778arithmeticconformationdecompositiondelay in wireshandshakepipelineverificationweak causality |
| spellingShingle | Alex Kushnerov Sergey Bystrov Signal Transition Graphs for Asynchronous Data Path Circuits Моделирование и анализ информационных систем arithmetic conformation decomposition delay in wires handshake pipeline verification weak causality |
| title | Signal Transition Graphs for Asynchronous Data Path Circuits |
| title_full | Signal Transition Graphs for Asynchronous Data Path Circuits |
| title_fullStr | Signal Transition Graphs for Asynchronous Data Path Circuits |
| title_full_unstemmed | Signal Transition Graphs for Asynchronous Data Path Circuits |
| title_short | Signal Transition Graphs for Asynchronous Data Path Circuits |
| title_sort | signal transition graphs for asynchronous data path circuits |
| topic | arithmetic conformation decomposition delay in wires handshake pipeline verification weak causality |
| url | https://www.mais-journal.ru/jour/article/view/1778 |
| work_keys_str_mv | AT alexkushnerov signaltransitiongraphsforasynchronousdatapathcircuits AT sergeybystrov signaltransitiongraphsforasynchronousdatapathcircuits |