Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage
The process of taking a new semiconductor device from the lab to the factory involves a lot of time, funds and manpower, a large portion of which is spent on device yield improvement. In recent years new methods have been tried to rapidly improve yields and using machine learning (ML) algorithms is...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10975036/ |
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| _version_ | 1849729609258500096 |
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| author | Chunshan Wang Zizhao Ma Yuxuan Zhu Chensheng Jin Dongyu Chen Chuxin Zhang Yining Chen Wenzhong Bao Yufeng Xie |
| author_facet | Chunshan Wang Zizhao Ma Yuxuan Zhu Chensheng Jin Dongyu Chen Chuxin Zhang Yining Chen Wenzhong Bao Yufeng Xie |
| author_sort | Chunshan Wang |
| collection | DOAJ |
| description | The process of taking a new semiconductor device from the lab to the factory involves a lot of time, funds and manpower, a large portion of which is spent on device yield improvement. In recent years new methods have been tried to rapidly improve yields and using machine learning (ML) algorithms is one option. However, they usually require a large dataset, which is often unavailable at the device research stage, emerging semiconductors (e.g., 2D materials) are extremely costly to pilot. In this paper, we propose a yield diagnosis and tuning scheme based on ensemble learning and Bayesian optimization, which demonstrate outstanding performance even with a limited data volume. We use real 2-D semiconductor device fabrication process data for scheme evaluation. Experimental results show that the algorithm for yield prediction has achieved regression fitting results whose mean absolute error (MAE) is no more than 8 points and explained variance (EVAR) is no less than 0.62, this indicates that the model fits well on this dataset. We also remanufactured a batch of devices based on the yield tuning recommendations to validate the effectiveness of our approach. The test results indicated a final yield score of 86 points, after evaluating several key indicators such as mobility and hysteresis, resulting in a 62% improvement. |
| format | Article |
| id | doaj-art-86c756b9b2a24190b2a47187b2113cc4 |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-86c756b9b2a24190b2a47187b2113cc42025-08-20T03:09:11ZengIEEEIEEE Access2169-35362025-01-0113789157892710.1109/ACCESS.2025.356376110975036Yield Diagnosis and Tuning for Emerging Semiconductors During Research StageChunshan Wang0https://orcid.org/0009-0009-3853-8475Zizhao Ma1Yuxuan Zhu2Chensheng Jin3https://orcid.org/0009-0009-5688-6289Dongyu Chen4Chuxin Zhang5Yining Chen6https://orcid.org/0000-0001-9302-6696Wenzhong Bao7https://orcid.org/0000-0002-3871-467XYufeng Xie8https://orcid.org/0000-0002-6541-2925State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaSchool of Integrated Circuits, Zhejiang University, Hangzhou, Zhejiang, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaState Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, ChinaThe process of taking a new semiconductor device from the lab to the factory involves a lot of time, funds and manpower, a large portion of which is spent on device yield improvement. In recent years new methods have been tried to rapidly improve yields and using machine learning (ML) algorithms is one option. However, they usually require a large dataset, which is often unavailable at the device research stage, emerging semiconductors (e.g., 2D materials) are extremely costly to pilot. In this paper, we propose a yield diagnosis and tuning scheme based on ensemble learning and Bayesian optimization, which demonstrate outstanding performance even with a limited data volume. We use real 2-D semiconductor device fabrication process data for scheme evaluation. Experimental results show that the algorithm for yield prediction has achieved regression fitting results whose mean absolute error (MAE) is no more than 8 points and explained variance (EVAR) is no less than 0.62, this indicates that the model fits well on this dataset. We also remanufactured a batch of devices based on the yield tuning recommendations to validate the effectiveness of our approach. The test results indicated a final yield score of 86 points, after evaluating several key indicators such as mobility and hysteresis, resulting in a 62% improvement.https://ieeexplore.ieee.org/document/10975036/Semiconductor manufacturingyield diagnosisyield predictionyield tuningBayesian optimization |
| spellingShingle | Chunshan Wang Zizhao Ma Yuxuan Zhu Chensheng Jin Dongyu Chen Chuxin Zhang Yining Chen Wenzhong Bao Yufeng Xie Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage IEEE Access Semiconductor manufacturing yield diagnosis yield prediction yield tuning Bayesian optimization |
| title | Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage |
| title_full | Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage |
| title_fullStr | Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage |
| title_full_unstemmed | Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage |
| title_short | Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage |
| title_sort | yield diagnosis and tuning for emerging semiconductors during research stage |
| topic | Semiconductor manufacturing yield diagnosis yield prediction yield tuning Bayesian optimization |
| url | https://ieeexplore.ieee.org/document/10975036/ |
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