Dynamic Surrogate Optimization of Vertically Stacked Nanosheet FET Based on Gaussian Process Regression

While speed improvements are pivotal for advancing modern transistor technologies and ensuring faster computational performance, the tradeoffs with other critical electrical properties, such as threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math...

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Bibliographic Details
Main Authors: Christofer N. Yalung, Doldet Tantraviwat
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/11018400/
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