Dynamic Surrogate Optimization of Vertically Stacked Nanosheet FET Based on Gaussian Process Regression
While speed improvements are pivotal for advancing modern transistor technologies and ensuring faster computational performance, the tradeoffs with other critical electrical properties, such as threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11018400/ |
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| Summary: | While speed improvements are pivotal for advancing modern transistor technologies and ensuring faster computational performance, the tradeoffs with other critical electrical properties, such as threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula>) and off-current (<inline-formula> <tex-math notation="LaTeX">$I_{OFF}$ </tex-math></inline-formula>), are often overlooked. These tradeoffs can significantly impact the overall device performance. The design of vertically stacked n-type and p-type nanosheet FETs (NSFETs) was applied using a dynamic surrogate optimization-gaussian process regression (DSO-GPR) with batch assessment and halting conditions. A vertically stacked silicon-based system is created and refined. Source extension (<inline-formula> <tex-math notation="LaTeX">$S_{ext}$ </tex-math></inline-formula>), drain extension (<inline-formula> <tex-math notation="LaTeX">$D_{ex\mathrm {t}}$ </tex-math></inline-formula>), gate length (<inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula>), nanosheet height (NSh), nanosheet width (NSw), and number of fin (nfin) make up the input variables. In addition to applying normalization to make the weight assignment to the goal functions easier, a penalty component was incorporated to manage the <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula>. This study demonstrates the effectiveness of the DSO-GPR framework in optimizing NSFET-based inverter designs by balancing speed, <inline-formula> <tex-math notation="LaTeX">$I_{OFF}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula>. Among the three evaluated cases, case 1 achieved the fastest propagation delay (1.05 ps) due to higher <inline-formula> <tex-math notation="LaTeX">$I_{ON}$ </tex-math></inline-formula> and lower <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula>, albeit with increased <inline-formula> <tex-math notation="LaTeX">$I_{OFF}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> mismatch. Case 2 provided a balanced trade-off, significantly reducing <inline-formula> <tex-math notation="LaTeX">$I_{OFF}$ </tex-math></inline-formula> while maintaining a competitive delay of 1.25 ps and achieving <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> matching at 0.11 V for both n-type and p-type NSFETs. The optimum parameters for n-type are <inline-formula> <tex-math notation="LaTeX">${L} _{g}$ </tex-math></inline-formula> = 5 nm, <inline-formula> <tex-math notation="LaTeX">$N_{Sh} = 9$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">$N_{Sw} = 42$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">$S_{ext} = 3$ </tex-math></inline-formula> nm and <inline-formula> <tex-math notation="LaTeX">$D_{ext} = 4$ </tex-math></inline-formula> nm, nfin = 5; for p-type, <inline-formula> <tex-math notation="LaTeX">$L_{g} = 7$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">$N_{Sh} = 10$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">$N_{Sw} = 42$ </tex-math></inline-formula> nm, <inline-formula> <tex-math notation="LaTeX">$S_{ext} = 3$ </tex-math></inline-formula> nm and <inline-formula> <tex-math notation="LaTeX">$D_{ext} = 3$ </tex-math></inline-formula> nm, nfin = 5. Case 3 minimized leakage at the cost of delay, highlighting the trade-off between power and performance. These results validate the framework’s adaptability and automation, with performance-based stopping criteria that balance accuracy and computational efficiency. |
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| ISSN: | 2169-3536 |