Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs
In this paper, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned. Further, solutions proposed so far are addressed and a new CPU architecture is introduced. The proposed a...
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| Format: | Article |
| Language: | English |
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Yaroslavl State University
2015-04-01
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| Series: | Моделирование и анализ информационных систем |
| Subjects: | |
| Online Access: | https://www.mais-journal.ru/jour/article/view/243 |
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| _version_ | 1849240810657153024 |
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| author | Maria S. Komar V. Petrov K. Borunova D. Moltchanov E. Koucheryavy |
| author_facet | Maria S. Komar V. Petrov K. Borunova D. Moltchanov E. Koucheryavy |
| author_sort | Maria S. Komar |
| collection | DOAJ |
| description | In this paper, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned. Further, solutions proposed so far are addressed and a new CPU architecture is introduced. The proposed architecture is based on wireless cache access that enables a reliable interaction between cores in multicore CPUs using terahertz band, 0.1-10THz. The presented architecture addresses the scalability problem of existing processors and may potentially allow to scale them to tens of cores. As in-depth analysis of the applicability of the suggested architecture requires accurate prediction of traffic in current and next generations of processors, we consider a set of approaches for traffic estimation in modern CPUs discussing their benefits and drawbacks. The authors identify traffic measurements by using existing software tools as the most promising approach for traffic estimation, and they use Intel Performance Counter Monitor for this purpose. Three types of CPU loads are considered including two artificial tests and background system load. For each load type the amount of data transmitted through the L2-L3 interface is reported for various input parameters including the number of active cores and their dependences on the number of cores and operational frequency. |
| format | Article |
| id | doaj-art-813770c2e2d04cd98ab6dff052c4ddab |
| institution | Kabale University |
| issn | 1818-1015 2313-5417 |
| language | English |
| publishDate | 2015-04-01 |
| publisher | Yaroslavl State University |
| record_format | Article |
| series | Моделирование и анализ информационных систем |
| spelling | doaj-art-813770c2e2d04cd98ab6dff052c4ddab2025-08-20T04:00:26ZengYaroslavl State UniversityМоделирование и анализ информационных систем1818-10152313-54172015-04-0122223824710.18255/1818-1015-2015-2-238-247236Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUsMaria S. Komar0V. Petrov1K. Borunova2D. Moltchanov3E. Koucheryavy4P.G. Demidov Yaroslavl State University; Tampere University of TechnologyThe Bonch-Bruevich Saint-Petersburg State University of TelecommunicationsThe Bonch-Bruevich Saint-Petersburg State University of TelecommunicationsTampere University of TechnologyTampere University of TechnologyIn this paper, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned. Further, solutions proposed so far are addressed and a new CPU architecture is introduced. The proposed architecture is based on wireless cache access that enables a reliable interaction between cores in multicore CPUs using terahertz band, 0.1-10THz. The presented architecture addresses the scalability problem of existing processors and may potentially allow to scale them to tens of cores. As in-depth analysis of the applicability of the suggested architecture requires accurate prediction of traffic in current and next generations of processors, we consider a set of approaches for traffic estimation in modern CPUs discussing their benefits and drawbacks. The authors identify traffic measurements by using existing software tools as the most promising approach for traffic estimation, and they use Intel Performance Counter Monitor for this purpose. Three types of CPU loads are considered including two artificial tests and background system load. For each load type the amount of data transmitted through the L2-L3 interface is reported for various input parameters including the number of active cores and their dependences on the number of cores and operational frequency.https://www.mais-journal.ru/jour/article/view/243multicore cpuswireless network on chipwnocbroadband communication systems |
| spellingShingle | Maria S. Komar V. Petrov K. Borunova D. Moltchanov E. Koucheryavy Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs Моделирование и анализ информационных систем multicore cpus wireless network on chip wnoc broadband communication systems |
| title | Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs |
| title_full | Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs |
| title_fullStr | Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs |
| title_full_unstemmed | Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs |
| title_short | Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs |
| title_sort | data rate estimation for wireless core to cache communication in multicore cpus |
| topic | multicore cpus wireless network on chip wnoc broadband communication systems |
| url | https://www.mais-journal.ru/jour/article/view/243 |
| work_keys_str_mv | AT mariaskomar datarateestimationforwirelesscoretocachecommunicationinmulticorecpus AT vpetrov datarateestimationforwirelesscoretocachecommunicationinmulticorecpus AT kborunova datarateestimationforwirelesscoretocachecommunicationinmulticorecpus AT dmoltchanov datarateestimationforwirelesscoretocachecommunicationinmulticorecpus AT ekoucheryavy datarateestimationforwirelesscoretocachecommunicationinmulticorecpus |