Reconfigurable versatile integrated photonic computing chip

Abstract With the rapid development of information technology, artificial intelligence and large-scale models have exhibited exceptional performance and widespread applications. Photonic hardware offers a promising solution to meet the growing demands for computational power and energy efficiency. R...

Full description

Saved in:
Bibliographic Details
Main Authors: Yufei Wang, Kun Liao, Kuo Zhang, Zhuochen Du, Ze Wang, Bo Ni, Tianyu Xu, Shuai Feng, Yan Yang, Qi-Fan Yang, Quan Sun, Xiaoyong Hu, Qihuang Gong
Format: Article
Language:English
Published: SpringerOpen 2025-08-01
Series:eLight
Subjects:
Online Access:https://doi.org/10.1186/s43593-025-00098-6
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Abstract With the rapid development of information technology, artificial intelligence and large-scale models have exhibited exceptional performance and widespread applications. Photonic hardware offers a promising solution to meet the growing demands for computational power and energy efficiency. Researchers have aimed to develop an efficient integrated photonic computing chip capable of supporting a wide range of application scenarios in both static and dynamic temporal domains. However, with several mainstream photonic components already well-developed, achieving fundamental breakthroughs at the level of basic computing units remains highly challenging. Here, we report a novel algorithm-hardware co-design strategy that enables in situ reconfigurability across diverse neural network models, all within a unified photonic configuration. We unlock the intrinsic capabilities of a compact cross-waveguide coupled microring component to natively support both static and dynamic temporal tasks. As a proof of concept, we experimentally integrated a turnkey soliton microcomb as the light source on the photonic computing platform, demonstrating the realization of fully connected, convolutional, and recurrent neural network models within a unified structure. The chip achieves area computing efficiency of up to 2.45 TOPS/mm2 for 208 tunable components. We evaluate the performance of the proposed chip by implementing image classification tasks on the MNIST and CIFAR-10 datasets, achieving measured test accuracies of 92.93% and 56.57%, respectively. Sentiment analysis on the IMDB dataset achieves a measured test accuracy of 80.81%. Furthermore, speech recognition is implemented by combining three neural networks within a scaled-up architecture. This work addresses the challenges of performing versatile computations on integrated photonic platforms, offering a promising solution for chip-integrated multifunctional photonic information processing.
ISSN:2097-1710
2662-8643