A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems
Modern Dynamic Random Access Memory (DRAM) banks are characterized by their ability to work in parallel, enabling concurrent servicing of multiple memory accesses through the interleaved DRAM banks. This attractive feature is supported in modern DRAM systems by employing large-sized pages to exploit...
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| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10778429/ |
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