Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions
To address growing data processing demands, traditional von Neumann architectures face increased power consumption and delay issues. In response, this paper presents a novel latch-based hybrid CMOS/MTJ content-addressable memory (TCAM) designed to perform Boolean logic, as well as full adder (FA) an...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10926925/ |
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| author | Zahra Mehdizadeh Taheri Sayed Masoud Sayedi Mohammad Hossein Moaiyeri |
| author_facet | Zahra Mehdizadeh Taheri Sayed Masoud Sayedi Mohammad Hossein Moaiyeri |
| author_sort | Zahra Mehdizadeh Taheri |
| collection | DOAJ |
| description | To address growing data processing demands, traditional von Neumann architectures face increased power consumption and delay issues. In response, this paper presents a novel latch-based hybrid CMOS/MTJ content-addressable memory (TCAM) designed to perform Boolean logic, as well as full adder (FA) and full subtractor (FS) operations, within a computing-in-memory (CIM) architecture. The proposed cell efficiently compares 4-bit encoded data in TCAM mode while supporting 8-bit data processing in computing mode, improving area efficiency. Additionally, the reduced number of active paths between the power supply and ground during the read phase significantly lowers power consumption. Complemented by peripheral circuits, a scalable array architecture has been developed to demonstrate the system’s feasibility. Post-layout simulations using 40 nm technology in Cadence Virtuoso and HSPICE show that the proposed design reduces power consumption and PDP by up to 35% in TCAM mode and up to 65% in COMPUTING mode compared to previous solutions. Furthermore, Monte Carlo simulations confirm the design’s robust resilience to process variations, highlighting its potential for reliable, energy-efficient operation. Also, the suggested design in the presence of temperature variations is investigated, and PDP results for temperatures range 0° C to 100° C show design resilience. In addition, our results indicate that the proposed strategy significantly reduces power consumption in neural network applications compared to its counterparts. |
| format | Article |
| id | doaj-art-7d71180041b0445f8763699db928fa2f |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-7d71180041b0445f8763699db928fa2f2025-08-20T03:40:51ZengIEEEIEEE Access2169-35362025-01-0113490764909110.1109/ACCESS.2025.355141110926925Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic FunctionsZahra Mehdizadeh Taheri0https://orcid.org/0009-0006-2024-1540Sayed Masoud Sayedi1https://orcid.org/0000-0002-3733-5694Mohammad Hossein Moaiyeri2https://orcid.org/0000-0001-9711-7923Department of Electrical and Computing Engineering, Isfahan University of Technology, Isfahan, IranDepartment of Electrical and Computing Engineering, Isfahan University of Technology, Isfahan, IranFaculty of Electrical Engineering, Shahid Beheshti University, Tehran, IranTo address growing data processing demands, traditional von Neumann architectures face increased power consumption and delay issues. In response, this paper presents a novel latch-based hybrid CMOS/MTJ content-addressable memory (TCAM) designed to perform Boolean logic, as well as full adder (FA) and full subtractor (FS) operations, within a computing-in-memory (CIM) architecture. The proposed cell efficiently compares 4-bit encoded data in TCAM mode while supporting 8-bit data processing in computing mode, improving area efficiency. Additionally, the reduced number of active paths between the power supply and ground during the read phase significantly lowers power consumption. Complemented by peripheral circuits, a scalable array architecture has been developed to demonstrate the system’s feasibility. Post-layout simulations using 40 nm technology in Cadence Virtuoso and HSPICE show that the proposed design reduces power consumption and PDP by up to 35% in TCAM mode and up to 65% in COMPUTING mode compared to previous solutions. Furthermore, Monte Carlo simulations confirm the design’s robust resilience to process variations, highlighting its potential for reliable, energy-efficient operation. Also, the suggested design in the presence of temperature variations is investigated, and PDP results for temperatures range 0° C to 100° C show design resilience. In addition, our results indicate that the proposed strategy significantly reduces power consumption in neural network applications compared to its counterparts.https://ieeexplore.ieee.org/document/10926925/Content addressable memory (CAM)Boolean logicfull adder (FA) and full subtractor (FS)computing in memory (CIM)process variation |
| spellingShingle | Zahra Mehdizadeh Taheri Sayed Masoud Sayedi Mohammad Hossein Moaiyeri Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions IEEE Access Content addressable memory (CAM) Boolean logic full adder (FA) and full subtractor (FS) computing in memory (CIM) process variation |
| title | Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions |
| title_full | Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions |
| title_fullStr | Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions |
| title_full_unstemmed | Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions |
| title_short | Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions |
| title_sort | spintronic content addressable memory with integrated boolean logic and arithmetic functions |
| topic | Content addressable memory (CAM) Boolean logic full adder (FA) and full subtractor (FS) computing in memory (CIM) process variation |
| url | https://ieeexplore.ieee.org/document/10926925/ |
| work_keys_str_mv | AT zahramehdizadehtaheri spintroniccontentaddressablememorywithintegratedbooleanlogicandarithmeticfunctions AT sayedmasoudsayedi spintroniccontentaddressablememorywithintegratedbooleanlogicandarithmeticfunctions AT mohammadhosseinmoaiyeri spintroniccontentaddressablememorywithintegratedbooleanlogicandarithmeticfunctions |