An efficient algorithmic framework to minimize the summand matrix in binary multiplication
Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usag...
Saved in:
| Main Authors: | Amit Verma, Manish Prateek, Shiv Naresh Shivhare, Thipendra P. Singh, Anuj Kumar, Rakesh Ranjan, Rahul Priyadarshi |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Taylor & Francis Group
2025-10-01
|
| Series: | Automatika |
| Subjects: | |
| Online Access: | https://www.tandfonline.com/doi/10.1080/00051144.2025.2526261 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
High Performance Low Latency 16Ã16 bit Booth Multiplier using Novel 4-2 Compressor Structure
by: Ali Rahnamaei, et al.
Published: (2024-02-01) -
Generation of Gray Codes Through the Rough Identity–Summand Graph of Filters of A Rough bi–Heyting Algebra
by: Praba Bashyam, et al.
Published: (2025-06-01) -
Design of Radix-8 Unsigned Bit Pair Recoding Algorithm-Based Floating-Point Multiplier for Neural Network Computations
by: J. Jean Jenifer Nesam, et al.
Published: (2025-01-01) -
A cross-language perspective on the MAIDAN-concept
by: Yehorova Olesia, et al.
Published: (2017-12-01) -
A cross-language perspective on the MAIDAN-concept
by: Olesia Yehorova, et al.
Published: (2025-01-01)