An efficient algorithmic framework to minimize the summand matrix in binary multiplication
Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usag...
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| Format: | Article |
| Language: | English |
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Taylor & Francis Group
2025-10-01
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| Series: | Automatika |
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| Online Access: | https://www.tandfonline.com/doi/10.1080/00051144.2025.2526261 |
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| author | Amit Verma Manish Prateek Shiv Naresh Shivhare Thipendra P. Singh Anuj Kumar Rakesh Ranjan Rahul Priyadarshi |
| author_facet | Amit Verma Manish Prateek Shiv Naresh Shivhare Thipendra P. Singh Anuj Kumar Rakesh Ranjan Rahul Priyadarshi |
| author_sort | Amit Verma |
| collection | DOAJ |
| description | Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments. |
| format | Article |
| id | doaj-art-76f9d2f387664e7999568925793ee708 |
| institution | Kabale University |
| issn | 0005-1144 1848-3380 |
| language | English |
| publishDate | 2025-10-01 |
| publisher | Taylor & Francis Group |
| record_format | Article |
| series | Automatika |
| spelling | doaj-art-76f9d2f387664e7999568925793ee7082025-08-20T03:50:07ZengTaylor & Francis GroupAutomatika0005-11441848-33802025-10-01664223110.1080/00051144.2025.2526261An efficient algorithmic framework to minimize the summand matrix in binary multiplicationAmit Verma0Manish Prateek1Shiv Naresh Shivhare2Thipendra P. Singh3Anuj Kumar4Rakesh Ranjan5Rahul Priyadarshi6School of Computer Science, UPES, Dehradun, IndiaComputer Science and Engineering, DBS Global University, Dehradun, IndiaSchool of Computer Science Engineering and Technology, Bennett University, Greater Noida, IndiaSchool of Computer Science Engineering and Technology, Bennett University, Greater Noida, IndiaDepartment of Computer Science, Doon University, Dehradun, IndiaSchool of Computer Science, UPES, Dehradun, IndiaFaculty of Engineering and Technology, ITER, Siksha ‘O’ Anusandhan (Deemed to Be University), Bhubaneswar, Odisha, IndiaBinary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments.https://www.tandfonline.com/doi/10.1080/00051144.2025.2526261Binary multiplicationlatency optimizationmultipliersummand reductionBooth’s algorithmhardware efficiency |
| spellingShingle | Amit Verma Manish Prateek Shiv Naresh Shivhare Thipendra P. Singh Anuj Kumar Rakesh Ranjan Rahul Priyadarshi An efficient algorithmic framework to minimize the summand matrix in binary multiplication Automatika Binary multiplication latency optimization multiplier summand reduction Booth’s algorithm hardware efficiency |
| title | An efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| title_full | An efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| title_fullStr | An efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| title_full_unstemmed | An efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| title_short | An efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| title_sort | efficient algorithmic framework to minimize the summand matrix in binary multiplication |
| topic | Binary multiplication latency optimization multiplier summand reduction Booth’s algorithm hardware efficiency |
| url | https://www.tandfonline.com/doi/10.1080/00051144.2025.2526261 |
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