Research of a carry chain TDC and its tap method
A time to digital converter(TDC) is implemented using carry chains in Xilinx Kinex-7 FPGA. FPGA-TDC is calibrated bin-by-bin through the code density calibration method. In the calibration process, it is found that different carry chain tap modes will lead to different code widths and nonlinearity o...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2022-04-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000148319 |
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