VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation
We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessar...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2011/936712 |
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| Summary: | We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the
hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss
the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping
to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our
measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a
distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating
the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for
crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power
supply–properties that are considered highly desirable for future technology nodes. |
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| ISSN: | 2090-0147 2090-0155 |