A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing
This article introduces a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET) cell operating in the charge domain, marking a significant advancement in nonvolatile memory (NVM) and compute-in-memory (CIM). Traditionally, NVMs, such as FeFETs or resistive R...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10750057/ |
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| author | Nellie Laleni Franz Muller Gonzalo Cunarro Thomas Kampfe Taekwang Jang |
| author_facet | Nellie Laleni Franz Muller Gonzalo Cunarro Thomas Kampfe Taekwang Jang |
| author_sort | Nellie Laleni |
| collection | DOAJ |
| description | This article introduces a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET) cell operating in the charge domain, marking a significant advancement in nonvolatile memory (NVM) and compute-in-memory (CIM). Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing. |
| format | Article |
| id | doaj-art-6daf969d26964832acc23a7f0e494d23 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-6daf969d26964832acc23a7f0e494d232025-01-24T00:02:10ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-011015316010.1109/JXCDC.2024.349561210750057A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN ProcessingNellie Laleni0https://orcid.org/0000-0002-2445-9989Franz Muller1https://orcid.org/0000-0002-6564-9121Gonzalo Cunarro2https://orcid.org/0009-0006-8999-7506Thomas Kampfe3https://orcid.org/0000-0002-4672-8676Taekwang Jang4https://orcid.org/0000-0002-4651-0677Fraunhofer IPMS, Dresden, GermanyFraunhofer IPMS, Dresden, GermanyFraunhofer IPMS, Dresden, GermanyFraunhofer IPMS, Dresden, GermanyETHZ, Zürich, SwitzerlandThis article introduces a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET) cell operating in the charge domain, marking a significant advancement in nonvolatile memory (NVM) and compute-in-memory (CIM). Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.https://ieeexplore.ieee.org/document/10750057/1FeFET-1Capacitance (1F1C)artificial intelligence (AI) acceleratorcharge domain computingcompute-in-memory (CIM)ferroelectric field-effect transistor (FeFET)multilevel memory cells |
| spellingShingle | Nellie Laleni Franz Muller Gonzalo Cunarro Thomas Kampfe Taekwang Jang A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1FeFET-1Capacitance (1F1C) artificial intelligence (AI) accelerator charge domain computing compute-in-memory (CIM) ferroelectric field-effect transistor (FeFET) multilevel memory cells |
| title | A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing |
| title_full | A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing |
| title_fullStr | A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing |
| title_full_unstemmed | A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing |
| title_short | A High-Efficiency Charge-Domain Compute-in-Memory 1F1C Macro Using 2-bit FeFET Cells for DNN Processing |
| title_sort | high efficiency charge domain compute in memory 1f1c macro using 2 bit fefet cells for dnn processing |
| topic | 1FeFET-1Capacitance (1F1C) artificial intelligence (AI) accelerator charge domain computing compute-in-memory (CIM) ferroelectric field-effect transistor (FeFET) multilevel memory cells |
| url | https://ieeexplore.ieee.org/document/10750057/ |
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