Simulation of Crosstalk in High-Speed Multi-Chip Modules
Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection architectures are presented with emphasis given to the dependence of crosstalk and signal delay on the geometries and dielectric constants of the insulating layers as well as on the widt...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
1995-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/1995/24575 |
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| Summary: | Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection
architectures are presented with emphasis given to the dependence of crosstalk and signal
delay on the geometries and dielectric constants of the insulating layers as well as on the widths and
separations of the conductors. The results indicate that signal delay and crosstalk may be reduced by
using low εr values for the dielectrics and that crosstalk may be also reduced by reducing the conductor-to-ground wire separation which simultaneously neutralises the role of εr value on crosstalk and line
impedance. |
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| ISSN: | 0882-7516 1563-5031 |