Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and...

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Bibliographic Details
Main Authors: Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Strain engineering
gate-all-around CMOS
neural compact model
circuit performance
Online Access:https://ieeexplore.ieee.org/document/10680295/
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