Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach
Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10680295/ |
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| author | Ji Hwan Lee Kihwan Kim Kyungjin Rim Soogine Chong Hyunbo Cho Saeroonter Oh |
| author_facet | Ji Hwan Lee Kihwan Kim Kyungjin Rim Soogine Chong Hyunbo Cho Saeroonter Oh |
| author_sort | Ji Hwan Lee |
| collection | DOAJ |
| description | Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence. |
| format | Article |
| id | doaj-art-6c071d2c300e4f238f314d4c7ad003f4 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-6c071d2c300e4f238f314d4c7ad003f42025-01-28T00:00:44ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011277077410.1109/JEDS.2024.345987210680295Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling ApproachJi Hwan Lee0Kihwan Kim1Kyungjin Rim2Soogine Chong3Hyunbo Cho4https://orcid.org/0009-0006-0425-5301Saeroonter Oh5https://orcid.org/0000-0003-4281-6879Department of Electronic and Electrical Engineering, Hanyang University, Ansan, Republic of KoreaDepartment of Electronic and Electrical Engineering, Hanyang University, Ansan, Republic of KoreaResearch and Development Center, Alsemy Inc., Seoul, Republic of KoreaResearch and Development Center, Alsemy Inc., Seoul, Republic of KoreaResearch and Development Center, Alsemy Inc., Seoul, Republic of KoreaDepartment of Electronic and Electrical Engineering, Hanyang University, Ansan, Republic of KoreaImpact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.https://ieeexplore.ieee.org/document/10680295/Strain engineeringgate-all-around CMOSneural compact modelcircuit performance |
| spellingShingle | Ji Hwan Lee Kihwan Kim Kyungjin Rim Soogine Chong Hyunbo Cho Saeroonter Oh Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach IEEE Journal of the Electron Devices Society Strain engineering gate-all-around CMOS neural compact model circuit performance |
| title | Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach |
| title_full | Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach |
| title_fullStr | Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach |
| title_full_unstemmed | Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach |
| title_short | Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach |
| title_sort | impact of strain on sub 3 nm gate all around cmos logic circuit performance using a neural compact modeling approach |
| topic | Strain engineering gate-all-around CMOS neural compact model circuit performance |
| url | https://ieeexplore.ieee.org/document/10680295/ |
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