APA (7th ed.) Citation

Lee, J. H., Kim, K., Rim, K., Chong, S., Cho, H., & Oh, S. Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach. IEEE.

Chicago Style (17th ed.) Citation

Lee, Ji Hwan, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, and Saeroonter Oh. Impact of Strain on Sub-3 Nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach. IEEE.

MLA (9th ed.) Citation

Lee, Ji Hwan, et al. Impact of Strain on Sub-3 Nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach. IEEE.