Dynamic Clock Tree Balancing Algorithm: Achieving Enhanced Performance Efficiency in Asic Design
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| Main Authors: | J Praveen Kumar, G. Sudhagar |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Polish Information Processing Society
2025-05-01
|
| Series: | Annals of computer science and information systems |
| Online Access: | https://annals-csis.org/Volume_42/drp/pdf/06.pdf |
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