Towards Fast Implementation of Complex RNS Components on FPGAs

The efficient hardware implementation of RNS particularly on field program-mable gate array (FPGA) is very important due to the use of FPGAs in some modern computing systems to achieve flexibility and low time-to-market. The residue number system (RNS) with its inherent parallelism can also be used...

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Main Authors: Sabbagh Molahosseini Amir, Alsadat Emrani Azadeh
Format: Article
Language:Russian
Published: North-Caucasus Federal University 2022-09-01
Series:Наука. Инновации. Технологии
Subjects:
Online Access:https://scienceit.elpub.ru/jour/article/view/429
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author Sabbagh Molahosseini Amir
Alsadat Emrani Azadeh
author_facet Sabbagh Molahosseini Amir
Alsadat Emrani Azadeh
author_sort Sabbagh Molahosseini Amir
collection DOAJ
description The efficient hardware implementation of RNS particularly on field program-mable gate array (FPGA) is very important due to the use of FPGAs in some modern computing systems to achieve flexibility and low time-to-market. The residue number system (RNS) with its inherent parallelism can also be used to enhance the performance of implementation of comput-ing algorithms on FPGAs. However, complex RNS operations such as residue to binary (reverse) conversion, sign detection, scaling, magnitude comparison and overflow detection have not been efficiently implemented on FPGAs until now. In this work, we try to address an approach to increase the speed of residue to binary conversion implementation on FPGAs using parallel-prefix adders. This can be a first step towards fast implementation of complex RNS operations on FPGAs, since residue to binary conversion can also be used to solve other difficult RNS operations.
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publisher North-Caucasus Federal University
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series Наука. Инновации. Технологии
spelling doaj-art-677593be3c9e46158e118bca88c6182a2025-08-20T03:19:11ZrusNorth-Caucasus Federal UniversityНаука. Инновации. Технологии2308-47582022-09-01048695428Towards Fast Implementation of Complex RNS Components on FPGAsSabbagh Molahosseini Amir0Alsadat Emrani Azadeh1Islamic Azad UniversityIslamic Azad UniversityThe efficient hardware implementation of RNS particularly on field program-mable gate array (FPGA) is very important due to the use of FPGAs in some modern computing systems to achieve flexibility and low time-to-market. The residue number system (RNS) with its inherent parallelism can also be used to enhance the performance of implementation of comput-ing algorithms on FPGAs. However, complex RNS operations such as residue to binary (reverse) conversion, sign detection, scaling, magnitude comparison and overflow detection have not been efficiently implemented on FPGAs until now. In this work, we try to address an approach to increase the speed of residue to binary conversion implementation on FPGAs using parallel-prefix adders. This can be a first step towards fast implementation of complex RNS operations on FPGAs, since residue to binary conversion can also be used to solve other difficult RNS operations.https://scienceit.elpub.ru/jour/article/view/429residue number system (rns)field programmable gate array fpga)parallel prefix addersсистема остаточных классов (rns)программируе-мая вентильная матрица (fpga)параллельный сумматор
spellingShingle Sabbagh Molahosseini Amir
Alsadat Emrani Azadeh
Towards Fast Implementation of Complex RNS Components on FPGAs
Наука. Инновации. Технологии
residue number system (rns)
field programmable gate array fpga)
parallel prefix adders
система остаточных классов (rns)
программируе-мая вентильная матрица (fpga)
параллельный сумматор
title Towards Fast Implementation of Complex RNS Components on FPGAs
title_full Towards Fast Implementation of Complex RNS Components on FPGAs
title_fullStr Towards Fast Implementation of Complex RNS Components on FPGAs
title_full_unstemmed Towards Fast Implementation of Complex RNS Components on FPGAs
title_short Towards Fast Implementation of Complex RNS Components on FPGAs
title_sort towards fast implementation of complex rns components on fpgas
topic residue number system (rns)
field programmable gate array fpga)
parallel prefix adders
система остаточных классов (rns)
программируе-мая вентильная матрица (fpga)
параллельный сумматор
url https://scienceit.elpub.ru/jour/article/view/429
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