Static Switching Dynamic Buffer Circuit
We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS tech...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | Journal of Engineering |
| Online Access: | http://dx.doi.org/10.1155/2013/646214 |
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| author | A. K. Pandey R. A. Mishra R. K. Nagaria |
| author_facet | A. K. Pandey R. A. Mishra R. K. Nagaria |
| author_sort | A. K. Pandey |
| collection | DOAJ |
| description | We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits. |
| format | Article |
| id | doaj-art-6497003225174950bf6e660102a2e46b |
| institution | Kabale University |
| issn | 2314-4904 2314-4912 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Engineering |
| spelling | doaj-art-6497003225174950bf6e660102a2e46b2025-02-03T01:07:25ZengWileyJournal of Engineering2314-49042314-49122013-01-01201310.1155/2013/646214646214Static Switching Dynamic Buffer CircuitA. K. Pandey0R. A. Mishra1R. K. Nagaria2Department of Electronics and Communication, MNNIT, Allahabad 211004, IndiaDepartment of Electronics and Communication, MNNIT, Allahabad 211004, IndiaDepartment of Electronics and Communication, MNNIT, Allahabad 211004, IndiaWe proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.http://dx.doi.org/10.1155/2013/646214 |
| spellingShingle | A. K. Pandey R. A. Mishra R. K. Nagaria Static Switching Dynamic Buffer Circuit Journal of Engineering |
| title | Static Switching Dynamic Buffer Circuit |
| title_full | Static Switching Dynamic Buffer Circuit |
| title_fullStr | Static Switching Dynamic Buffer Circuit |
| title_full_unstemmed | Static Switching Dynamic Buffer Circuit |
| title_short | Static Switching Dynamic Buffer Circuit |
| title_sort | static switching dynamic buffer circuit |
| url | http://dx.doi.org/10.1155/2013/646214 |
| work_keys_str_mv | AT akpandey staticswitchingdynamicbuffercircuit AT ramishra staticswitchingdynamicbuffercircuit AT rknagaria staticswitchingdynamicbuffercircuit |