Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization pr...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2012/763572 |
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| _version_ | 1850157966412480512 |
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| author | Chi-Jih Shih Chih-Yao Hsu Chun-Yi Kuo James Li Jiann-Chyi Rau Krishnendu Chakrabarty |
| author_facet | Chi-Jih Shih Chih-Yao Hsu Chun-Yi Kuo James Li Jiann-Chyi Rau Krishnendu Chakrabarty |
| author_sort | Chi-Jih Shih |
| collection | DOAJ |
| description | Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC. |
| format | Article |
| id | doaj-art-62b4ddb1d5cb4fa898c1c85e32a7d035 |
| institution | OA Journals |
| issn | 0882-7516 1563-5031 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj-art-62b4ddb1d5cb4fa898c1c85e32a7d0352025-08-20T02:24:00ZengWileyActive and Passive Electronic Components0882-75161563-50312012-01-01201210.1155/2012/763572763572Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional ICChi-Jih Shih0Chih-Yao Hsu1Chun-Yi Kuo2James Li3Jiann-Chyi Rau4Krishnendu Chakrabarty5Department of Electrical Engineering, National Taiwan University, Taipei 10617, TaiwanDepartment of Electrical Engineering, National Taiwan University, Taipei 10617, TaiwanDepartment of Electrical Engineering, National Taiwan University, Taipei 10617, TaiwanDepartment of Electrical Engineering, National Taiwan University, Taipei 10617, TaiwanDepartment of Electrical Engineering, Tamkang University, New Taipei City 25137, TaiwanDepartment of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USATesting is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.http://dx.doi.org/10.1155/2012/763572 |
| spellingShingle | Chi-Jih Shih Chih-Yao Hsu Chun-Yi Kuo James Li Jiann-Chyi Rau Krishnendu Chakrabarty Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC Active and Passive Electronic Components |
| title | Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC |
| title_full | Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC |
| title_fullStr | Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC |
| title_full_unstemmed | Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC |
| title_short | Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC |
| title_sort | thermal aware test schedule and tam co optimization for three dimensional ic |
| url | http://dx.doi.org/10.1155/2012/763572 |
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