A Flexible and Parallel Hardware Accelerator for Forward and Inverse Number Theoretic Transform

A Flexible and Parallel Hardware Accelerator for Forward and Inverse Number Theoretic Transform

This paper demonstrates an efficient and flexible hardware accelerator for polynomial multiplication using number theoretic transform (NTT). The proposed architecture considers flexibility and performance requirements at the same time. Flexibility is achieved by computing the following three operati...

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Bibliographic Details
Main Authors: Muhammad Rashid, Safiullah Khan, Omar S. Sonbul, Seong Oun Hwang
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
FPGA
hardware architecture
number theoretic transform
parallel and flexible
Online Access:https://ieeexplore.ieee.org/document/10772085/
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