TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices
Modern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To imp...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10839381/ |
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