TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices
Modern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To imp...
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2025-01-01
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| author | Tran Dai Duong Young Seung Kim Jae Young Hur |
| author_facet | Tran Dai Duong Young Seung Kim Jae Young Hur |
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| description | Modern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To improve TLB utilization, a number of TLB coalescing schemes have recently been reported. The TLB coalescing schemes exploit the contiguous memory allocation and can efficiently coalesce the contiguous virtual-to-physical page mappings into a single TLB entry. Accordingly, TLB coalescing schemes efficiently utilize TLB entries, reduce page-table walks, and can improve the memory system performance. However, the conventional page table is still organized in the page level and contains redundant page information. Subsequently, it is difficult for operating system to effectively represent the block-level contiguity in the page table and it is difficult for TLB coalescing hardware to exploit the contiguity. In this work, to improve the memory system performance, we propose a range compression technique in a page table. In the presented page-table entry, the redundant page attributes are removed and multiple block mappings are added. Considering high-bandwidth memory intensive mobile workloads, we conduct the performance experiments. As a result, the presented scheme can significantly perform better than the traditional scheme and the reference TLB coalescing schemes. |
| format | Article |
| id | doaj-art-58c00aac7adb4f57bac574a67e0bc0b6 |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| spelling | doaj-art-58c00aac7adb4f57bac574a67e0bc0b62025-08-20T02:47:10ZengIEEEIEEE Access2169-35362025-01-0113126231263310.1109/ACCESS.2025.352894510839381TLB Coalescing With Range Compressed Page Table for Embedded I/O DevicesTran Dai Duong0https://orcid.org/0000-0001-9268-5614Young Seung Kim1Jae Young Hur2https://orcid.org/0000-0003-4151-908XDepartment of Electronic Engineering, Jeju National University, Jeju-si, South KoreaMetaCNI, Jeju-si, South KoreaDepartment of Electronic Engineering, Jeju National University, Jeju-si, South KoreaModern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To improve TLB utilization, a number of TLB coalescing schemes have recently been reported. The TLB coalescing schemes exploit the contiguous memory allocation and can efficiently coalesce the contiguous virtual-to-physical page mappings into a single TLB entry. Accordingly, TLB coalescing schemes efficiently utilize TLB entries, reduce page-table walks, and can improve the memory system performance. However, the conventional page table is still organized in the page level and contains redundant page information. Subsequently, it is difficult for operating system to effectively represent the block-level contiguity in the page table and it is difficult for TLB coalescing hardware to exploit the contiguity. In this work, to improve the memory system performance, we propose a range compression technique in a page table. In the presented page-table entry, the redundant page attributes are removed and multiple block mappings are added. Considering high-bandwidth memory intensive mobile workloads, we conduct the performance experiments. As a result, the presented scheme can significantly perform better than the traditional scheme and the reference TLB coalescing schemes.https://ieeexplore.ieee.org/document/10839381/Page tablecompressionaddress translationtranslation look-aside buffermemory management |
| spellingShingle | Tran Dai Duong Young Seung Kim Jae Young Hur TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices IEEE Access Page table compression address translation translation look-aside buffer memory management |
| title | TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices |
| title_full | TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices |
| title_fullStr | TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices |
| title_full_unstemmed | TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices |
| title_short | TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices |
| title_sort | tlb coalescing with range compressed page table for embedded i o devices |
| topic | Page table compression address translation translation look-aside buffer memory management |
| url | https://ieeexplore.ieee.org/document/10839381/ |
| work_keys_str_mv | AT trandaiduong tlbcoalescingwithrangecompressedpagetableforembeddediodevices AT youngseungkim tlbcoalescingwithrangecompressedpagetableforembeddediodevices AT jaeyounghur tlbcoalescingwithrangecompressedpagetableforembeddediodevices |