Improved Design of Bit Synchronization Clock Extraction in Digital Communication System
An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit. By using a newly added digital filter between the phase detector and the controller, the phase difference pul...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2018-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2018/8024168 |
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