Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with th...
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| Format: | Article |
| Language: | English |
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Wiley
2018-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2018/3276159 |
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| _version_ | 1832548730529644544 |
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| author | Bahram N. Uchevler Kjetil Svarstad |
| author_facet | Bahram N. Uchevler Kjetil Svarstad |
| author_sort | Bahram N. Uchevler |
| collection | DOAJ |
| description | With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform. |
| format | Article |
| id | doaj-art-53c1d6dc482049869ab992a1b870e637 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2018-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-53c1d6dc482049869ab992a1b870e6372025-02-03T06:13:15ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092018-01-01201810.1155/2018/32761593276159Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming AbstractionsBahram N. Uchevler0Kjetil Svarstad1Department of Electronics and Telecommunication, Norwegian University of Science and Technology, NorwayDepartment of Electronics and Telecommunication, Norwegian University of Science and Technology, NorwayWith the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.http://dx.doi.org/10.1155/2018/3276159 |
| spellingShingle | Bahram N. Uchevler Kjetil Svarstad Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions International Journal of Reconfigurable Computing |
| title | Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions |
| title_full | Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions |
| title_fullStr | Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions |
| title_full_unstemmed | Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions |
| title_short | Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions |
| title_sort | modelling and assertion based verification of run time reconfigurable designs using functional programming abstractions |
| url | http://dx.doi.org/10.1155/2018/3276159 |
| work_keys_str_mv | AT bahramnuchevler modellingandassertionbasedverificationofruntimereconfigurabledesignsusingfunctionalprogrammingabstractions AT kjetilsvarstad modellingandassertionbasedverificationofruntimereconfigurabledesignsusingfunctionalprogrammingabstractions |