Solar Photovoltaic Diagnostic System with Logic Verification and Integrated Circuit Design for Fabrication
Solar photovoltaic (PV) panels are the best solution to reduce greenhouse gas emissions by fossil fuel combustion, with global capability now exceeding 714 GW due to rapid technological advances in solar panels (SPs). However, SPs’ efficiency and lifespan remain limited due to the absence of advance...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-05-01
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| Series: | Solar |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2673-9941/5/2/24 |
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| Summary: | Solar photovoltaic (PV) panels are the best solution to reduce greenhouse gas emissions by fossil fuel combustion, with global capability now exceeding 714 GW due to rapid technological advances in solar panels (SPs). However, SPs’ efficiency and lifespan remain limited due to the absence of advanced fault-detection systems, and they are prone to short circuits (SC), open circuits (OC), and power degradation. Therefore, this large-scale production requires reliable, real-time fault diagnosis to maintain panel performance. However, traditional diagnostic methods implemented using MPPT, neural networks, or microcontroller-based systems often rely on complex computational algorithms and are not cost-effective. So, this paper proposes a diagnostic system composed of six functional blocks to address this issue. The proposed system was initially verified using an Intel DE-10 Lite FPGA board. Once its functionality was confirmed, an ASIC design was proposed for mass production, offering a significantly lower implementation cost and reduced hardware complexity than prior methods. Different circuit designs were developed for each of the six blocks. All designs were created using Cadence software and TSMC 180 nm technology files. The basic components used in these designs include PMOS transistors with 300 nm channel length and 2 µm width, NMOS transistors with 350 nm channel length and 2 µm width, as well as resistors and capacitors. Differential amplifiers with a gain of 40 dB were used for voltage and current sensing from the SP. The chip activation signal generator circuit was designed with an adjustable frequency and generated 120 MHz and 100 MHz signals in this work. The decision-making block, Logic Driver Circuit, was innovatively implemented using a reduced number of transistors. A custom memory block with a reset switch was also implemented to store the fault value detected at the SP. Finally, the proposed ASIC was implemented for fabrication, which is highly cost-effective in mass production and does not require complex computational stages. |
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| ISSN: | 2673-9941 |