Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools
The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alte...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2013-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2013/428078 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832558653266198528 |
|---|---|
| author | Bruno da Silva An Braeken Erik H. D’Hollander Abdellah Touhafi |
| author_facet | Bruno da Silva An Braeken Erik H. D’Hollander Abdellah Touhafi |
| author_sort | Bruno da Silva |
| collection | DOAJ |
| description | The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design space exploration due to design at high-level or analytical performance models which provide realistic performance expectations, potential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order to construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our proposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools, to maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize the design exploration of a class of window-based image processing applications using two different HLS tools. The results show the accuracy
of the model as well as its flexibility to be combined with any HLS tool. |
| format | Article |
| id | doaj-art-5165824cc9b546d089c6a80daab16db3 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-5165824cc9b546d089c6a80daab16db32025-02-03T01:31:52ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/428078428078Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis ToolsBruno da Silva0An Braeken1Erik H. D’Hollander2Abdellah Touhafi3INDI Department, Vrije Universiteit Brussel, 1050 Brussels, BelgiumINDI Department, Vrije Universiteit Brussel, 1050 Brussels, BelgiumELIS Department, Ghent University, 9000 Ghent, BelgiumINDI Department, Vrije Universiteit Brussel, 1050 Brussels, BelgiumThe potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design space exploration due to design at high-level or analytical performance models which provide realistic performance expectations, potential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order to construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our proposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools, to maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize the design exploration of a class of window-based image processing applications using two different HLS tools. The results show the accuracy of the model as well as its flexibility to be combined with any HLS tool.http://dx.doi.org/10.1155/2013/428078 |
| spellingShingle | Bruno da Silva An Braeken Erik H. D’Hollander Abdellah Touhafi Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools International Journal of Reconfigurable Computing |
| title | Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools |
| title_full | Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools |
| title_fullStr | Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools |
| title_full_unstemmed | Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools |
| title_short | Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools |
| title_sort | performance modeling for fpgas extending the roofline model with high level synthesis tools |
| url | http://dx.doi.org/10.1155/2013/428078 |
| work_keys_str_mv | AT brunodasilva performancemodelingforfpgasextendingtherooflinemodelwithhighlevelsynthesistools AT anbraeken performancemodelingforfpgasextendingtherooflinemodelwithhighlevelsynthesistools AT erikhdhollander performancemodelingforfpgasextendingtherooflinemodelwithhighlevelsynthesistools AT abdellahtouhafi performancemodelingforfpgasextendingtherooflinemodelwithhighlevelsynthesistools |