Automatic Pipelining and Vectorization of Scientific Code for FPGAs
There is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manual effort and is a major obstacle to wider FPGA adoption. We a...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2019-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2019/7348013 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832562668721930240 |
|---|---|
| author | Syed Waqar Nabi Wim Vanderbauwhede |
| author_facet | Syed Waqar Nabi Wim Vanderbauwhede |
| author_sort | Syed Waqar Nabi |
| collection | DOAJ |
| description | There is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manual effort and is a major obstacle to wider FPGA adoption. We are developing an automated optimizing compiler TyTra to overcome this obstacle. The TyTra flow aims to compile legacy Fortran code automatically for FPGA-based acceleration, while applying suitable optimizations. We present the flow with a focus on two key optimizations, automatic pipelining and vectorization. Our compiler frontend extracts patterns from legacy Fortran code that can be pipelined and vectorized. The backend first creates fine and coarse-grained pipelines and then automatically vectorizes both the memory access and the datapath based on a cost model, generating an OpenCL-HDL hybrid working solution for FPGA targets on the Amazon cloud. Our results show up to 4.2× performance improvement over baseline OpenCL code. |
| format | Article |
| id | doaj-art-50e03b9b7115497eb5d8c89dbf6d5a93 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2019-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-50e03b9b7115497eb5d8c89dbf6d5a932025-02-03T01:22:00ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092019-01-01201910.1155/2019/73480137348013Automatic Pipelining and Vectorization of Scientific Code for FPGAsSyed Waqar Nabi0Wim Vanderbauwhede1School of Computing Science, University of Glasgow, Glasgow, UKSchool of Computing Science, University of Glasgow, Glasgow, UKThere is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manual effort and is a major obstacle to wider FPGA adoption. We are developing an automated optimizing compiler TyTra to overcome this obstacle. The TyTra flow aims to compile legacy Fortran code automatically for FPGA-based acceleration, while applying suitable optimizations. We present the flow with a focus on two key optimizations, automatic pipelining and vectorization. Our compiler frontend extracts patterns from legacy Fortran code that can be pipelined and vectorized. The backend first creates fine and coarse-grained pipelines and then automatically vectorizes both the memory access and the datapath based on a cost model, generating an OpenCL-HDL hybrid working solution for FPGA targets on the Amazon cloud. Our results show up to 4.2× performance improvement over baseline OpenCL code.http://dx.doi.org/10.1155/2019/7348013 |
| spellingShingle | Syed Waqar Nabi Wim Vanderbauwhede Automatic Pipelining and Vectorization of Scientific Code for FPGAs International Journal of Reconfigurable Computing |
| title | Automatic Pipelining and Vectorization of Scientific Code for FPGAs |
| title_full | Automatic Pipelining and Vectorization of Scientific Code for FPGAs |
| title_fullStr | Automatic Pipelining and Vectorization of Scientific Code for FPGAs |
| title_full_unstemmed | Automatic Pipelining and Vectorization of Scientific Code for FPGAs |
| title_short | Automatic Pipelining and Vectorization of Scientific Code for FPGAs |
| title_sort | automatic pipelining and vectorization of scientific code for fpgas |
| url | http://dx.doi.org/10.1155/2019/7348013 |
| work_keys_str_mv | AT syedwaqarnabi automaticpipeliningandvectorizationofscientificcodeforfpgas AT wimvanderbauwhede automaticpipeliningandvectorizationofscientificcodeforfpgas |