Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops
Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had be...
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| Format: | Article |
| Language: | English |
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Wiley
2020-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2020/8108591 |
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| author | Lamjed Touil Abdelaziz Hamdi Ismail Gassoumi Abdellatif Mtibaa |
| author_facet | Lamjed Touil Abdelaziz Hamdi Ismail Gassoumi Abdellatif Mtibaa |
| author_sort | Lamjed Touil |
| collection | DOAJ |
| description | Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design. |
| format | Article |
| id | doaj-art-4ed1daeb5dff40d28398c1d186458a84 |
| institution | OA Journals |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2020-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-4ed1daeb5dff40d28398c1d186458a842025-08-20T02:05:35ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552020-01-01202010.1155/2020/81085918108591Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-FlopsLamjed Touil0Abdelaziz Hamdi1Ismail Gassoumi2Abdellatif Mtibaa3Laboratory of Electronics and Microelectronics, University of Monastir, Monastir, TunisiaPrince Research Laboratory, ISITC, University of Sousse, Sousse, TunisiaLaboratory of Electronics and Microelectronics, University of Monastir, Monastir, TunisiaLaboratory of Electronics and Microelectronics, University of Monastir, Monastir, TunisiaOptimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.http://dx.doi.org/10.1155/2020/8108591 |
| spellingShingle | Lamjed Touil Abdelaziz Hamdi Ismail Gassoumi Abdellatif Mtibaa Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops Journal of Electrical and Computer Engineering |
| title | Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops |
| title_full | Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops |
| title_fullStr | Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops |
| title_full_unstemmed | Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops |
| title_short | Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops |
| title_sort | design of low power structural fir filter using data driven clock gating and multibit flip flops |
| url | http://dx.doi.org/10.1155/2020/8108591 |
| work_keys_str_mv | AT lamjedtouil designoflowpowerstructuralfirfilterusingdatadrivenclockgatingandmultibitflipflops AT abdelazizhamdi designoflowpowerstructuralfirfilterusingdatadrivenclockgatingandmultibitflipflops AT ismailgassoumi designoflowpowerstructuralfirfilterusingdatadrivenclockgatingandmultibitflipflops AT abdellatifmtibaa designoflowpowerstructuralfirfilterusingdatadrivenclockgatingandmultibitflipflops |