Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach
This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of impl...
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10990136/ |
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| author | Joseph Anthony Prathap Mithileysh Sathiyanarayanan |
| author_facet | Joseph Anthony Prathap Mithileysh Sathiyanarayanan |
| author_sort | Joseph Anthony Prathap |
| collection | DOAJ |
| description | This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of implementation. When utilized in real applications, the attack in the bit transmission either at the encryption or at the decryption might affect its authentication and security. This demands automatic fault identification within the blowfish algorithm using a modified Decision tree. This work includes attack induction and identification of the same using the developed modified decision tree-based equality checker circuit. The proposed method involves the development of an equality-checker-based decision tree algorithm to form 12 sections for the 16 iterations from the encryption and decryption process of the blowfish algorithm. The FPGA device implements the proposed method to validate the real-time feasibility. Also, the System on Chip IC layout is developed for the proposed method to analyze the parameters of power and area using the EDA tools. The utilization of FPGA in indicating the attack of the blowfish algorithm is evaluated for its high-performance capability that has low latency and higher throughput for the 64-bit design resolution. |
| format | Article |
| id | doaj-art-4bf7feaa02194187a76d1da3ec620f95 |
| institution | OA Journals |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-4bf7feaa02194187a76d1da3ec620f952025-08-20T02:34:36ZengIEEEIEEE Access2169-35362025-01-0113905919060010.1109/ACCESS.2025.356765910990136Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree ApproachJoseph Anthony Prathap0https://orcid.org/0000-0001-9643-5954Mithileysh Sathiyanarayanan1https://orcid.org/0000-0002-8598-1949Department of Electrical and Electronic Engineering, City St George’s, University of London, London, England, U.K.Department of Electrical and Electronic Engineering, City St George’s, University of London, London, England, U.K.This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of implementation. When utilized in real applications, the attack in the bit transmission either at the encryption or at the decryption might affect its authentication and security. This demands automatic fault identification within the blowfish algorithm using a modified Decision tree. This work includes attack induction and identification of the same using the developed modified decision tree-based equality checker circuit. The proposed method involves the development of an equality-checker-based decision tree algorithm to form 12 sections for the 16 iterations from the encryption and decryption process of the blowfish algorithm. The FPGA device implements the proposed method to validate the real-time feasibility. Also, the System on Chip IC layout is developed for the proposed method to analyze the parameters of power and area using the EDA tools. The utilization of FPGA in indicating the attack of the blowfish algorithm is evaluated for its high-performance capability that has low latency and higher throughput for the 64-bit design resolution.https://ieeexplore.ieee.org/document/10990136/Blowfish cryptography algorithmfault identificationdecision tree algorithmfield programmable gate arraysystem-on-chip design |
| spellingShingle | Joseph Anthony Prathap Mithileysh Sathiyanarayanan Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach IEEE Access Blowfish cryptography algorithm fault identification decision tree algorithm field programmable gate array system-on-chip design |
| title | Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach |
| title_full | Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach |
| title_fullStr | Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach |
| title_full_unstemmed | Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach |
| title_short | Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach |
| title_sort | fault detection in blowfish algorithm using fpga based modified decision tree approach |
| topic | Blowfish cryptography algorithm fault identification decision tree algorithm field programmable gate array system-on-chip design |
| url | https://ieeexplore.ieee.org/document/10990136/ |
| work_keys_str_mv | AT josephanthonyprathap faultdetectioninblowfishalgorithmusingfpgabasedmodifieddecisiontreeapproach AT mithileyshsathiyanarayanan faultdetectioninblowfishalgorithmusingfpgabasedmodifieddecisiontreeapproach |