Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications
This study presents an efficient and high‐speed very large‐scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2m) with Gaussian normal basis representation. The proposed implementation is a low‐cost structure constructed by one digit‐serial...
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| Format: | Article |
| Language: | English |
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Wiley
2017-11-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/iet-cds.2017.0110 |
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| author | Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi |
| author_facet | Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi |
| author_sort | Bahram Rashidi |
| collection | DOAJ |
| description | This study presents an efficient and high‐speed very large‐scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2m) with Gaussian normal basis representation. The proposed implementation is a low‐cost structure constructed by one digit‐serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low‐cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost. |
| format | Article |
| id | doaj-art-4b1764e9b6ea4bfabf713446f0f492ca |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2017-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-4b1764e9b6ea4bfabf713446f0f492ca2025-08-20T03:36:39ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982017-11-0111656857810.1049/iet-cds.2017.0110Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applicationsBahram Rashidi0Sayed Masoud Sayedi1Reza Rezaeian Farashahi2Department of Electrical EngineeringUniversity of Ayatollah Ozma BoroujerdiBoroujerd69199‐69411IranDepartment of Electrical & Computer EngineeringIsfahan University of TechnologyIsfahan84156‐83111IranDept. of Mathematical SciencesIsfahan University of TechnologyIsfahan84156‐83111IranThis study presents an efficient and high‐speed very large‐scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2m) with Gaussian normal basis representation. The proposed implementation is a low‐cost structure constructed by one digit‐serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low‐cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.https://doi.org/10.1049/iet-cds.2017.0110full-custom hardware implementationpoint multiplication schedulingbinary Edwards curvesapplication-specific integrated circuit elliptic curve cryptosystem applicationshigh-speed very large-scale integration implementationbinary finite field GF(2m) |
| spellingShingle | Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications IET Circuits, Devices and Systems full-custom hardware implementation point multiplication scheduling binary Edwards curves application-specific integrated circuit elliptic curve cryptosystem applications high-speed very large-scale integration implementation binary finite field GF(2m) |
| title | Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications |
| title_full | Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications |
| title_fullStr | Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications |
| title_full_unstemmed | Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications |
| title_short | Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications |
| title_sort | full custom hardware implementation of point multiplication on binary edwards curves for application specific integrated circuit elliptic curve cryptosystem applications |
| topic | full-custom hardware implementation point multiplication scheduling binary Edwards curves application-specific integrated circuit elliptic curve cryptosystem applications high-speed very large-scale integration implementation binary finite field GF(2m) |
| url | https://doi.org/10.1049/iet-cds.2017.0110 |
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