An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS
As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop b...
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| Format: | Article |
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IEEE
2024-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10606254/ |
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| author | Jiliang Liu Huidong Zhao Zhi Li Kangning Wang Shushan Qiao |
| author_facet | Jiliang Liu Huidong Zhao Zhi Li Kangning Wang Shushan Qiao |
| author_sort | Jiliang Liu |
| collection | DOAJ |
| description | As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop by eliminating all redundant charges and discharges. Floating nodes are compensated by transistor-level optimization, which also enables a fully static and contention-free FF circuit design. The proposed FF is implemented in 55 nm CMOS technology. Post-layout simulation results demonstrate that at a supply voltage of 0.6 V and 10% data activity, the proposed circuit consumes only 0.153 fJ/cycle. |
| format | Article |
| id | doaj-art-4ac145ed080b44299889c73be52e8647 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-4ac145ed080b44299889c73be52e86472025-01-16T00:02:09ZengIEEEIEEE Access2169-35362024-01-011218789218789810.1109/ACCESS.2024.343216210606254An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOSJiliang Liu0https://orcid.org/0000-0002-0942-864XHuidong Zhao1Zhi Li2https://orcid.org/0009-0000-5529-1421Kangning Wang3Shushan Qiao4https://orcid.org/0000-0002-9102-2111Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaAs essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop by eliminating all redundant charges and discharges. Floating nodes are compensated by transistor-level optimization, which also enables a fully static and contention-free FF circuit design. The proposed FF is implemented in 55 nm CMOS technology. Post-layout simulation results demonstrate that at a supply voltage of 0.6 V and 10% data activity, the proposed circuit consumes only 0.153 fJ/cycle.https://ieeexplore.ieee.org/document/10606254/CMOS digital circuitsflip-flop (FF)low voltage operationultra-low-powertrue-single-phase-clocked (TSPC) |
| spellingShingle | Jiliang Liu Huidong Zhao Zhi Li Kangning Wang Shushan Qiao An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS IEEE Access CMOS digital circuits flip-flop (FF) low voltage operation ultra-low-power true-single-phase-clocked (TSPC) |
| title | An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS |
| title_full | An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS |
| title_fullStr | An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS |
| title_full_unstemmed | An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS |
| title_short | An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS |
| title_sort | ultra low power static contention free 25 transistor true single phase clocked flip flop in 55 nm cmos |
| topic | CMOS digital circuits flip-flop (FF) low voltage operation ultra-low-power true-single-phase-clocked (TSPC) |
| url | https://ieeexplore.ieee.org/document/10606254/ |
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